gpu: nvgpu: Add Top as a unit

NVHSCLK registers used by NVLINK IP are part of dev_top
hardware headers. This patch adds "Top" as a separate
unit and exposes HALs to access dev_top registers. The top
unit contains top-level configuration information and any
extra registers or features that do not fit into another block's
feature set.

JIRA NVGPU-1053
JIRA NVGPU-966

Change-Id: Id9a43d4a1c5397959897a242ea97a39a1b95f916
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803632
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -44,7 +44,8 @@ nvgpu-y += common/bus/bus_gk20a.o \
 	common/therm/therm_gv11b.o \
 	common/fuse/fuse_gm20b.o \
 	common/fuse/fuse_gp10b.o \
-	common/fuse/fuse_gp106.o
+	common/fuse/fuse_gp106.o \
+	common/top/top_gv100.o
 
 # Linux specific parts of nvgpu.
 nvgpu-y += \

drivers/gpu/nvgpu/Makefile.sources

@@ -77,6 +77,7 @@ srcs :=	os/posix/nvgpu.c \
 	common/fuse/fuse_gm20b.c \
 	common/fuse/fuse_gp10b.c \
 	common/fuse/fuse_gp106.c \
+	common/top/top_gv100.c \
 	common/enabled.c \
 	common/pramin.c \
 	common/semaphore.c \

drivers/gpu/nvgpu/common/top/top_gv100.c

@@ -0,0 +1,66 @@
+/*
+ * GV100 TOP UNIT
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+
+#include "gk20a/gk20a.h"
+#include "top_gv100.h"
+
+#include <nvgpu/hw/gv100/hw_top_gv100.h>
+
+u32 gv100_top_get_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g)
+{
+	u32 reg;
+
+	reg = nvgpu_readl(g, top_nvhsclk_ctrl_r());
+	return top_nvhsclk_ctrl_e_clk_nvl_v(reg);
+}
+
+void gv100_top_set_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g, u32 val)
+{
+	u32 reg;
+
+	reg = nvgpu_readl(g, top_nvhsclk_ctrl_r());
+	reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(),
+				top_nvhsclk_ctrl_e_clk_nvl_f(val));
+	nvgpu_writel(g, top_nvhsclk_ctrl_r(), reg);
+}
+
+u32 gv100_top_get_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g)
+{
+	u32 reg;
+
+	reg = nvgpu_readl(g, top_nvhsclk_ctrl_r());
+	return top_nvhsclk_ctrl_swap_clk_nvl_v(reg);
+}
+
+void gv100_top_set_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g, u32 val)
+{
+	u32 reg;
+
+	reg = nvgpu_readl(g, top_nvhsclk_ctrl_r());
+	reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(),
+				top_nvhsclk_ctrl_swap_clk_nvl_f(val));
+	nvgpu_writel(g, top_nvhsclk_ctrl_r(), reg);
+}

drivers/gpu/nvgpu/common/top/top_gv100.h

@@ -0,0 +1,37 @@
+/*
+ * GV100 TOP UNIT
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef TOP_GV100_H
+#define TOP_GV100_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+u32 gv100_top_get_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g);
+void gv100_top_set_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g, u32 val);
+u32 gv100_top_get_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g);
+void gv100_top_set_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g, u32 val);
+
+#endif

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -1314,7 +1314,12 @@ struct gpu_ops {
 		int (*shutdown)(struct gk20a *g);
 		int (*early_init)(struct gk20a *g);
 	} nvlink;
-
+	struct {
+		u32 (*get_nvhsclk_ctrl_e_clk_nvl)(struct gk20a *g);
+		void (*set_nvhsclk_ctrl_e_clk_nvl)(struct gk20a *g, u32 val);
+		u32 (*get_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g);
+		void (*set_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g, u32 val);
+	} top;
 	void (*semaphore_wakeup)(struct gk20a *g, bool post_events);
 };
 

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -44,6 +44,7 @@
 #include "common/fuse/fuse_gm20b.h"
 #include "common/fuse/fuse_gp10b.h"
 #include "common/fuse/fuse_gp106.h"
+#include "common/top/top_gv100.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -926,6 +927,16 @@ static const struct gpu_ops gv100_ops = {
 		.early_init = gv100_nvlink_early_init,
 	},
 #endif
+	.top = {
+		.get_nvhsclk_ctrl_e_clk_nvl =
+					gv100_top_get_nvhsclk_ctrl_e_clk_nvl,
+		.set_nvhsclk_ctrl_e_clk_nvl =
+					gv100_top_set_nvhsclk_ctrl_e_clk_nvl,
+		.get_nvhsclk_ctrl_swap_clk_nvl =
+					gv100_top_get_nvhsclk_ctrl_swap_clk_nvl,
+		.set_nvhsclk_ctrl_swap_clk_nvl =
+					gv100_top_set_nvhsclk_ctrl_swap_clk_nvl,
+	},
 	.chip_init_gpu_characteristics = gv100_init_gpu_characteristics,
 	.get_litter_value = gv100_get_litter_value,
 };
@@ -964,6 +975,7 @@ int gv100_init_hal(struct gk20a *g)
 	gops->priv_ring = gv100_ops.priv_ring;
 	gops->fuse = gv100_ops.fuse;
 	gops->nvlink = gv100_ops.nvlink;
+	gops->top = gv100_ops.top;
 
 	/* clocks */
 	gops->clk.init_clk_support = gv100_ops.clk.init_clk_support;

drivers/gpu/nvgpu/gv100/nvlink_gv100.c

@@ -1461,7 +1461,8 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask)
 	u32 i;
 	u32 links_off;
 	struct nvgpu_timeout timeout;
-	u32 pad_ctrl, swap_ctrl;
+	u32 pad_ctrl = 0;
+	u32 swap_ctrl = 0;
 	u32 pll_id;
 
 	reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r());
@@ -1469,10 +1470,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask)
 			trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(1));
 	gk20a_writel(g, trim_sys_nvlink_uphy_cfg_r(), reg);
 
-	reg = gk20a_readl(g, top_nvhsclk_ctrl_r());
+	if (g->ops.top.get_nvhsclk_ctrl_e_clk_nvl) {
-
+		pad_ctrl = g->ops.top.get_nvhsclk_ctrl_e_clk_nvl(g);
-	pad_ctrl = top_nvhsclk_ctrl_e_clk_nvl_v(reg);
+	}
-	swap_ctrl = top_nvhsclk_ctrl_swap_clk_nvl_v(reg);
+	if (g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl) {
+		swap_ctrl = g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl(g);
+	}
 
 	for_each_set_bit(i, &link_mask, 32) {
 		/* There are 3 PLLs for 6 links. We have 3 bits for each PLL.
@@ -1483,12 +1486,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask)
 		swap_ctrl |= BIT(pll_id);
 	}
 
-	reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(),
+	if (g->ops.top.set_nvhsclk_ctrl_e_clk_nvl) {
-			top_nvhsclk_ctrl_e_clk_nvl_f(pad_ctrl));
+		g->ops.top.set_nvhsclk_ctrl_e_clk_nvl(g, pad_ctrl);
-	reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(),
+	}
-		top_nvhsclk_ctrl_swap_clk_nvl_f(swap_ctrl));
+	if (g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl) {
-
+		g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl(g, swap_ctrl);
-	gk20a_writel(g, top_nvhsclk_ctrl_r(), reg);
+	}
 
 	for_each_set_bit(i, &link_mask, 32) {
 		reg = gk20a_readl(g, TRIM_SYS_NVLINK_CTRL(i));