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gpu: nvgpu: channel MISRA fix for Rule 21.2

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Rename
_gk20a_channel_get -> nvgpu_channel_get__func
gk20a_channel_get -> nvgpu_channel_get
_gk20a_channel_put -> nvgpu_channel_put__func
gk20a_channel_put -> nvgpu_channel_put
trace_gk20a_channel_get -> trace_nvgpu_channel_get
trace_gk20a_channel_put -> trace_nvgpu_channel_put

JIRA NVGPU-3388

Change-Id: I4e37adddbb5ce14aa18132722719ca2f73f1ba52
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114118
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-05-07 15:11:39 -07:00
committed by mobile promotions
parent 26d13b3b6b
commit 671f1c8a36
24 changed files with 103 additions and 105 deletions
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4
drivers/gpu/nvgpu/os/linux/debug_fifo.c
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@@ -86,7 +86,7 @@ static int gk20a_fifo_sched_debugfs_seq_show(
if (!test_bit(ch->chid, runlist->active_channels))
return ret;
if (gk20a_channel_get(ch)) {
if (nvgpu_channel_get(ch)) {
tsg = tsg_gk20a_from_ch(ch);
if (tsg)
@@ -99,7 +99,7 @@ static int gk20a_fifo_sched_debugfs_seq_show(
tsg->interleave_level,
nvgpu_gr_ctx_get_graphics_preemption_mode(tsg->gr_ctx),
nvgpu_gr_ctx_get_compute_preemption_mode(tsg->gr_ctx));
gk20a_channel_put(ch);
nvgpu_channel_put(ch);
}
return 0;
}