diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 3602b0f3a..42d5f8697 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -81,7 +81,7 @@ struct fifo_engine_info_gk20a *nvgpu_engine_get_active_eng_info( } u32 nvgpu_engine_get_ids(struct gk20a *g, - u32 engine_id[], u32 engine_id_sz, + u32 *engine_ids, u32 engine_id_sz, enum nvgpu_fifo_engine engine_enum) { struct fifo_gk20a *f = NULL; @@ -103,7 +103,7 @@ u32 nvgpu_engine_get_ids(struct gk20a *g, if (info->engine_enum == engine_enum) { if (instance_cnt < engine_id_sz) { - engine_id[instance_cnt] = active_engine_id; + engine_ids[instance_cnt] = active_engine_id; ++instance_cnt; } else { nvgpu_log_info(g, "warning engine_id table sz is small %d", @@ -114,7 +114,7 @@ u32 nvgpu_engine_get_ids(struct gk20a *g, return instance_cnt; } -bool nvgpu_engine_check_valid_eng_id(struct gk20a *g, u32 engine_id) +bool nvgpu_engine_check_valid_id(struct gk20a *g, u32 engine_id) { struct fifo_gk20a *f = NULL; u32 engine_id_idx; @@ -144,7 +144,7 @@ bool nvgpu_engine_check_valid_eng_id(struct gk20a *g, u32 engine_id) return valid; } -u32 nvgpu_engine_get_gr_eng_id(struct gk20a *g) +u32 nvgpu_engine_get_gr_id(struct gk20a *g) { u32 gr_engine_cnt = 0; u32 gr_engine_id = FIFO_INVAL_ENGINE_ID; @@ -177,7 +177,7 @@ u32 nvgpu_engine_interrupt_mask(struct gk20a *g) u32 eng_intr_mask = 0; unsigned int i; u32 active_engine_id = 0; - enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A; + enum nvgpu_fifo_engine engine_enum; for (i = 0; i < g->fifo.num_engines; i++) { u32 intr_mask; @@ -197,10 +197,10 @@ u32 nvgpu_engine_interrupt_mask(struct gk20a *g) return eng_intr_mask; } -u32 nvgpu_engine_get_all_ce_eng_reset_mask(struct gk20a *g) +u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g) { u32 reset_mask = 0; - enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A; + enum nvgpu_fifo_engine engine_enum; struct fifo_gk20a *f = NULL; u32 engine_id_idx; struct fifo_engine_info_gk20a *engine_info; diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c index 66cfe647c..7c1df455a 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c @@ -40,7 +40,7 @@ void gm20b_mc_isr_stall(struct gk20a *g) u32 mc_intr_0; u32 engine_id_idx; u32 active_engine_id = 0; - u32 engine_enum = NVGPU_ENGINE_INVAL_GK20A; + enum nvgpu_fifo_engine engine_enum; mc_intr_0 = g->ops.mc.intr_stall(g); @@ -89,7 +89,7 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) u32 mc_intr_1; u32 engine_id_idx; u32 active_engine_id = 0; - u32 engine_enum = NVGPU_ENGINE_INVAL_GK20A; + enum nvgpu_fifo_engine engine_enum; mc_intr_1 = g->ops.mc.intr_nonstall(g); @@ -247,7 +247,7 @@ void gm20b_mc_enable(struct gk20a *g, u32 units) void gm20b_mc_reset(struct gk20a *g, u32 units) { g->ops.mc.disable(g, units); - if ((units & nvgpu_engine_get_all_ce_eng_reset_mask(g)) != 0U) { + if ((units & nvgpu_engine_get_all_ce_reset_mask(g)) != 0U) { nvgpu_udelay(500); } else { nvgpu_udelay(20); diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c index c4c8568b8..983fcc014 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c @@ -96,7 +96,7 @@ void mc_gp10b_isr_stall(struct gk20a *g) u32 engine_id_idx; u32 active_engine_id = 0; - u32 engine_enum = NVGPU_ENGINE_INVAL_GK20A; + enum nvgpu_fifo_engine engine_enum; mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c index 9a1576550..88c5608d4 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c @@ -559,7 +559,7 @@ int nvgpu_pmu_init_bind_fecs(struct gk20a *g) nvgpu_log_fn(g, " "); - gr_engine_id = nvgpu_engine_get_gr_eng_id(g); + gr_engine_id = nvgpu_engine_get_gr_id(g); (void) memset(&cmd, 0, sizeof(struct pmu_cmd)); cmd.hdr.unit_id = PMU_UNIT_PG; @@ -600,7 +600,7 @@ void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g) u32 gr_engine_id; int err = 0; - gr_engine_id = nvgpu_engine_get_gr_eng_id(g); + gr_engine_id = nvgpu_engine_get_gr_id(g); (void) memset(&cmd, 0, sizeof(struct pmu_cmd)); cmd.hdr.unit_id = PMU_UNIT_PG; diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 9a8d9bf6d..27874546e 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c @@ -350,7 +350,7 @@ int gk20a_init_ce_support(struct gk20a *g) g->ce_app = ce_app; } - ce_reset_mask = nvgpu_engine_get_all_ce_eng_reset_mask(g); + ce_reset_mask = nvgpu_engine_get_all_ce_reset_mask(g); g->ops.mc.reset(g, ce_reset_mask); diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 9e0a9a677..6898df520 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -99,7 +99,7 @@ void nvgpu_report_host_error(struct gk20a *g, u32 inst, u32 gk20a_fifo_get_fast_ce_runlist_id(struct gk20a *g) { u32 ce_runlist_id = gk20a_fifo_get_gr_runlist_id(g); - enum nvgpu_fifo_engine engine_enum = NVGPU_ENGINE_INVAL_GK20A; + enum nvgpu_fifo_engine engine_enum; struct fifo_gk20a *f = NULL; u32 engine_id_idx; struct fifo_engine_info_gk20a *engine_info; @@ -1738,7 +1738,7 @@ bool gk20a_fifo_handle_sched_error(struct gk20a *g) engine_id = gk20a_fifo_get_failing_engine_data(g, &id, &is_tsg); /* could not find the engine - should never happen */ - if (!nvgpu_engine_check_valid_eng_id(g, engine_id)) { + if (!nvgpu_engine_check_valid_id(g, engine_id)) { nvgpu_err(g, "fifo sched error : 0x%08x, failed to find engine", sched_error); ret = false; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index da6cff510..371ecd5f1 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -246,7 +246,7 @@ int gr_gk20a_wait_idle(struct gk20a *g) nvgpu_log_fn(g, " "); - gr_engine_id = nvgpu_engine_get_gr_eng_id(g); + gr_engine_id = nvgpu_engine_get_gr_id(g); nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), NVGPU_TIMER_CPU_TIMER); @@ -4290,7 +4290,7 @@ int gk20a_gr_isr(struct gk20a *g) return 0; } - gr_engine_id = nvgpu_engine_get_gr_eng_id(g); + gr_engine_id = nvgpu_engine_get_gr_id(g); if (gr_engine_id != FIFO_INVAL_ENGINE_ID) { gr_engine_id = BIT32(gr_engine_id); } diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 70947ef24..703d3324f 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -67,7 +67,7 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, /* trigger faults for all bad engines */ for_each_set_bit(engine_id, &engine_ids, 32UL) { - if (!nvgpu_engine_check_valid_eng_id(g, engine_id)) { + if (!nvgpu_engine_check_valid_id(g, (u32)engine_id)) { nvgpu_err(g, "faulting unknown engine %ld", engine_id); } else { u32 mmu_id = gm20b_engine_id_to_mmu_id(g, diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 226168704..05357736a 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -923,7 +923,7 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g, u32 gr_engine_id; struct nvgpu_engine_status_info engine_status; - gr_engine_id = nvgpu_engine_get_gr_eng_id(g); + gr_engine_id = nvgpu_engine_get_gr_id(g); gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n", gk20a_readl(g, gr_status_r())); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 00985a52b..23a501e26 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1115,7 +1115,7 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g, u32 gr_engine_id; struct nvgpu_engine_status_info engine_status; - gr_engine_id = nvgpu_engine_get_gr_eng_id(g); + gr_engine_id = nvgpu_engine_get_gr_id(g); gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n", gk20a_readl(g, gr_status_r())); diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index ea1515e64..7c67a2d4e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1724,7 +1724,7 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g, u32 gr_engine_id; struct nvgpu_engine_status_info engine_status; - gr_engine_id = nvgpu_engine_get_gr_eng_id(g); + gr_engine_id = nvgpu_engine_get_gr_id(g); gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n", gk20a_readl(g, gr_status_r())); diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h index 67c588b85..9e9e62ae4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engines.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h @@ -29,7 +29,7 @@ struct gk20a; struct fifo_engine_info_gk20a; enum nvgpu_fifo_engine { - NVGPU_ENGINE_GR_GK20A = 0U, + NVGPU_ENGINE_GR_GK20A = 0U, NVGPU_ENGINE_GRCE_GK20A = 1U, NVGPU_ENGINE_ASYNC_CE_GK20A = 2U, NVGPU_ENGINE_INVAL_GK20A = 3U, @@ -42,13 +42,13 @@ struct fifo_engine_info_gk20a *nvgpu_engine_get_active_eng_info( struct gk20a *g, u32 engine_id); u32 nvgpu_engine_get_ids(struct gk20a *g, - u32 engine_id[], u32 engine_id_sz, + u32 *engine_ids, u32 engine_id_sz, enum nvgpu_fifo_engine engine_enum); -bool nvgpu_engine_check_valid_eng_id(struct gk20a *g, u32 engine_id); -u32 nvgpu_engine_get_gr_eng_id(struct gk20a *g); +bool nvgpu_engine_check_valid_id(struct gk20a *g, u32 engine_id); +u32 nvgpu_engine_get_gr_id(struct gk20a *g); u32 nvgpu_engine_interrupt_mask(struct gk20a *g); u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 act_eng_id); -u32 nvgpu_engine_get_all_ce_eng_reset_mask(struct gk20a *g); +u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g); #endif /*NVGPU_ENGINE_H*/ \ No newline at end of file diff --git a/drivers/gpu/nvgpu/os/linux/debug_fifo.c b/drivers/gpu/nvgpu/os/linux/debug_fifo.c index 93349d0eb..676ba9f43 100644 --- a/drivers/gpu/nvgpu/os/linux/debug_fifo.c +++ b/drivers/gpu/nvgpu/os/linux/debug_fifo.c @@ -70,7 +70,7 @@ static int gk20a_fifo_sched_debugfs_seq_show( int ret = SEQ_SKIP; u32 engine_id; - engine_id = nvgpu_engine_get_gr_eng_id(g); + engine_id = nvgpu_engine_get_gr_id(g); engine_info = (f->engine_info + engine_id); runlist_id = engine_info->runlist_id; runlist = &f->runlist_info[runlist_id];