From 6849526d7ff7a6d767295d1b04832c4b7f4d2eba Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 16 Sep 2019 18:03:10 +0530 Subject: [PATCH] gpu: nvgpu: compile out ECC feature override in safety Overriding of ECC feature is used only in Linux through device tree fuse overrides. It's not supported in QNX. Hence compile out below functions from safety build. nvgpu_gr_get_override_ecc_val() nvgpu_gr_override_ecc_val() Move nvgpu_gr_get_golden_image_ptr() under CONFIG_NVGPU_DEBUGGER Re-arrange all functions in gr_utils.c/h and move all non-safe functions towards end of file. Jira NVGPU-4028 Change-Id: Ie56fcf78c32a9b23d2e5f5b51701c5f8ccad62ec Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2199507 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: Seshendra Gadagottu Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr_priv.h | 2 + drivers/gpu/nvgpu/common/gr/gr_utils.c | 48 ++++++++++--------- .../nvgpu/hal/gr/init/gr_init_gv11b_fusa.c | 4 ++ drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h | 13 +++-- 4 files changed, 40 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr_priv.h b/drivers/gpu/nvgpu/common/gr/gr_priv.h index e040267b2..3090f47ad 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_priv.h +++ b/drivers/gpu/nvgpu/common/gr/gr_priv.h @@ -68,7 +68,9 @@ struct nvgpu_gr { void (*remove_support)(struct gk20a *g); bool sw_ready; +#ifdef CONFIG_NVGPU_NON_FUSA u32 fecs_feature_override_ecc_val; +#endif #ifdef CONFIG_NVGPU_CILP u32 cilp_preempt_pending_chid; diff --git a/drivers/gpu/nvgpu/common/gr/gr_utils.c b/drivers/gpu/nvgpu/common/gr/gr_utils.c index 1f848ed41..24a511957 100644 --- a/drivers/gpu/nvgpu/common/gr/gr_utils.c +++ b/drivers/gpu/nvgpu/common/gr/gr_utils.c @@ -33,12 +33,28 @@ struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g) return g->gr->falcon; } -struct nvgpu_gr_obj_ctx_golden_image *nvgpu_gr_get_golden_image_ptr( - struct gk20a *g) +struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g) { - return g->gr->golden_image; + return g->gr->config; } +struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g) +{ + return g->gr->intr; +} + +#ifdef CONFIG_NVGPU_NON_FUSA +u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g) +{ + return g->gr->fecs_feature_override_ecc_val; +} + +void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val) +{ + g->gr->fecs_feature_override_ecc_val = ecc_val; +} +#endif + #ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zcull *nvgpu_gr_get_zcull_ptr(struct gk20a *g) { @@ -51,16 +67,6 @@ struct nvgpu_gr_zbc *nvgpu_gr_get_zbc_ptr(struct gk20a *g) } #endif -struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g) -{ - return g->gr->config; -} - -struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g) -{ - return g->gr->intr; -} - #ifdef CONFIG_NVGPU_FECS_TRACE struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr( struct gk20a *g) @@ -69,16 +75,6 @@ struct nvgpu_gr_global_ctx_buffer_desc *nvgpu_gr_get_global_ctx_buffer_ptr( } #endif -u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g) -{ - return g->gr->fecs_feature_override_ecc_val; -} - -void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val) -{ - g->gr->fecs_feature_override_ecc_val = ecc_val; -} - #ifdef CONFIG_NVGPU_CILP u32 nvgpu_gr_get_cilp_preempt_pending_chid(struct gk20a *g) { @@ -93,6 +89,12 @@ void nvgpu_gr_clear_cilp_preempt_pending_chid(struct gk20a *g) #endif #ifdef CONFIG_NVGPU_DEBUGGER +struct nvgpu_gr_obj_ctx_golden_image *nvgpu_gr_get_golden_image_ptr( + struct gk20a *g) +{ + return g->gr->golden_image; +} + struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g) { return g->gr->hwpm_map; diff --git a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c index 4ad827c7a..60c7b92bf 100644 --- a/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c @@ -504,7 +504,9 @@ void gv11b_gr_init_tpc_mask(struct gk20a *g, u32 gpc_index, u32 pes_tpc_mask) int gv11b_gr_init_fs_state(struct gk20a *g) { u32 data; +#ifdef CONFIG_NVGPU_NON_FUSA u32 ecc_val; +#endif int err = 0; u32 ver = g->params.gpu_arch + g->params.gpu_impl; @@ -549,10 +551,12 @@ int gv11b_gr_init_fs_state(struct gk20a *g) gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); nvgpu_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); +#ifdef CONFIG_NVGPU_NON_FUSA ecc_val = nvgpu_gr_get_override_ecc_val(g); if (ecc_val != 0U) { nvgpu_writel(g, gr_fecs_feature_override_ecc_r(), ecc_val); } +#endif data = nvgpu_readl(g, gr_debug_0_r()); data = set_field(data, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h index 0ec68e9c4..80adf5e32 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_utils.h @@ -30,14 +30,17 @@ struct gk20a; struct nvgpu_gr_falcon; struct nvgpu_gr_obj_ctx_golden_image; struct nvgpu_gr_config; - +struct nvgpu_gr_intr; #ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zbc; struct nvgpu_gr_zcull; #endif +#ifdef CONFIG_NVGPU_DEBUGGER struct nvgpu_gr_hwpm_map; -struct nvgpu_gr_intr; +#endif +#ifdef CONFIG_NVGPU_FECS_TRACE struct nvgpu_gr_global_ctx_buffer_desc; +#endif static inline u32 nvgpu_gr_checksum_u32(u32 a, u32 b) { @@ -46,13 +49,13 @@ static inline u32 nvgpu_gr_checksum_u32(u32 a, u32 b) /* gr struct pointers */ struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g); -struct nvgpu_gr_obj_ctx_golden_image *nvgpu_gr_get_golden_image_ptr( - struct gk20a *g); struct nvgpu_gr_config *nvgpu_gr_get_config_ptr(struct gk20a *g); struct nvgpu_gr_intr *nvgpu_gr_get_intr_ptr(struct gk20a *g); +#ifdef CONFIG_NVGPU_NON_FUSA /* gr variables */ u32 nvgpu_gr_get_override_ecc_val(struct gk20a *g); void nvgpu_gr_override_ecc_val(struct gk20a *g, u32 ecc_val); +#endif #ifdef CONFIG_NVGPU_GRAPHICS struct nvgpu_gr_zcull *nvgpu_gr_get_zcull_ptr(struct gk20a *g); struct nvgpu_gr_zbc *nvgpu_gr_get_zbc_ptr(struct gk20a *g); @@ -62,6 +65,8 @@ u32 nvgpu_gr_get_cilp_preempt_pending_chid(struct gk20a *g); void nvgpu_gr_clear_cilp_preempt_pending_chid(struct gk20a *g); #endif #ifdef CONFIG_NVGPU_DEBUGGER +struct nvgpu_gr_obj_ctx_golden_image *nvgpu_gr_get_golden_image_ptr( + struct gk20a *g); struct nvgpu_gr_hwpm_map *nvgpu_gr_get_hwpm_map_ptr(struct gk20a *g); void nvgpu_gr_reset_falcon_ptr(struct gk20a *g); void nvgpu_gr_reset_golden_image_ptr(struct gk20a *g);