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gpu: nvgpu: gv11b+: set live pes mask

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This change is reading the live pes from the register
"gr_gpc0_gpm_pd_live_physical_pes_r" and set it to
"gr_gpc0_swdx_pes_mask_r".

Every PES needs at least a TPC to work. If any of the TPCs
are floorswept,the live PES mask is read from
"gr_gpc0_gpm_pd_live_physical_pes_r" and  the corresponding
active PES mask is updated in "gr_gpc0_swdx_pes_mask_r".

Bug 3677421

Change-Id: I899ac41c4a82beb3ce75c84ad57dcad262a49ba1
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2736560
(cherry picked from commit 85f2ceb3db6eeef925b49553f445d8cc31ec39da)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2759135
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Dinesh T
2022-06-28 20:13:13 +00:00
committed by mobile promotions
parent 8cb147aa88
commit 68976fbd22
14 changed files with 76 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -863,6 +863,16 @@ static int gr_init_support_impl(struct gk20a *g)
}
}
/*
* Enable this errata for all the chips from GV11B.
*/
if (nvgpu_is_errata_present(g, NVGPU_ERRATA_200075440)) {
if (g->ops.gr.config.set_live_pes_mask != NULL) {
g->ops.gr.config.set_live_pes_mask(g,
nvgpu_gr_config_get_gpc_count(gr->config));
}
}
/*
* Move sm id programming before loading ctxsw and gpccs firmwares. This
* is the actual sequence expected by ctxsw ucode.

2
drivers/gpu/nvgpu/hal/gr/config/gr_config_gv11b.h
View File

@@ -30,4 +30,6 @@ struct nvgpu_gr_config;
u32 gv11b_gr_config_get_gpc_pes_mask(struct gk20a *g,
struct nvgpu_gr_config *config, u32 gpc_index);
void gv11b_gr_config_set_live_pes_mask(struct gk20a *g,
u32 gpc_count);
#endif /* NVGPU_GR_CONFIG_GV11B_H */

31
drivers/gpu/nvgpu/hal/gr/config/gr_config_gv11b_fusa.c
View File

@@ -24,7 +24,7 @@
#include <nvgpu/io.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/gr.h>
#include "gr_config_gv11b.h"
#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
@@ -43,3 +43,32 @@ u32 gv11b_gr_config_get_gpc_pes_mask(struct gk20a *g,
return (~val) & nvgpu_safe_sub_u32(BIT32(pes_cnt), 1U);
}
void gv11b_gr_config_set_live_pes_mask(struct gk20a *g,
u32 gpc_count)
{
u32 pes_mask = 0U;
u32 temp_mask = 0U;
u32 offset = 0U;
u32 gpc_index = 0U;
for (gpc_index = 0U; gpc_index < gpc_count; gpc_index++) {
offset = nvgpu_gr_gpc_offset(g, gpc_index);
temp_mask = nvgpu_readl(g, gr_gpc0_gpm_pd_live_physical_pes_r()
+ offset);
temp_mask =
gr_gpc0_gpm_pd_live_physical_pes_gpc0_gpm_pd_live_physical_pes_mask_f(temp_mask);
temp_mask <<= (NUMBER_OF_BITS_COMPUTE_PES_MASK * gpc_index);
pes_mask = temp_mask | pes_mask;
}
/*
* When TPCs are floorswept, Corresponding PES mask needs to be updated
* in this register. For an example : If a GPC contains "x" TPCs and "y"
* PES. Every PES needs atleast a TPC to be enabled to work. If
* contiguous "x/y" TPCs are floorswept , then "y-1" PES will be active.
*/
for (gpc_index = 0U; gpc_index < gpc_count; gpc_index++) {
offset = nvgpu_gr_gpc_offset(g, gpc_index);
nvgpu_writel(g, gr_gpc0_swdx_pes_mask_r() + offset, pes_mask);
}
}

2
drivers/gpu/nvgpu/hal/init/hal_ga100.c
View File

@@ -528,6 +528,7 @@ static const struct gops_gr_ctxsw_prog ga100_ops_gr_ctxsw_prog = {
static const struct gops_gr_config ga100_ops_gr_config = {
.get_gpc_mask = gm20b_gr_config_get_gpc_mask,
.get_gpc_pes_mask = gv11b_gr_config_get_gpc_pes_mask,
.set_live_pes_mask = gv11b_gr_config_set_live_pes_mask,
.get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask,
.get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc,
.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
@@ -1864,6 +1865,7 @@ int ga100_init_hal(struct gk20a *g)
nvgpu_set_errata(g, NVGPU_ERRATA_200391931, true);
nvgpu_set_errata(g, NVGPU_ERRATA_SYNCPT_INVALID_ID_0, true);
nvgpu_set_errata(g, NVGPU_ERRATA_2557724, true);
nvgpu_set_errata(g, NVGPU_ERRATA_200075440, true);
if (gops->fuse.fuse_opt_sm_ttu_en(g) != 0U) {
nvgpu_set_enabled(g, NVGPU_SUPPORT_SM_TTU, true);

2
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -521,6 +521,7 @@ static const struct gops_gr_config ga10b_ops_gr_config = {
.get_gpc_mask = gm20b_gr_config_get_gpc_mask,
.get_gpc_tpc_mask = gm20b_gr_config_get_gpc_tpc_mask,
.get_gpc_pes_mask = gv11b_gr_config_get_gpc_pes_mask,
.set_live_pes_mask = gv11b_gr_config_set_live_pes_mask,
.get_gpc_rop_mask = ga10b_gr_config_get_gpc_rop_mask,
.get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc,
.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
@@ -1879,6 +1880,7 @@ int ga10b_init_hal(struct gk20a *g)
nvgpu_set_errata(g, NVGPU_ERRATA_SYNCPT_INVALID_ID_0, true);
nvgpu_set_errata(g, NVGPU_ERRATA_2557724, true);
nvgpu_set_errata(g, NVGPU_ERRATA_3524791, true);
nvgpu_set_errata(g, NVGPU_ERRATA_200075440, true);
nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -416,6 +416,7 @@ static const struct gops_gr_config gv11b_ops_gr_config = {
.get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc,
.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
.get_gpc_pes_mask = gv11b_gr_config_get_gpc_pes_mask,
.set_live_pes_mask = gv11b_gr_config_set_live_pes_mask,
.get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size,
.init_sm_id_table = gv100_gr_config_init_sm_id_table,
#ifdef CONFIG_NVGPU_GRAPHICS
@@ -1598,6 +1599,7 @@ int gv11b_init_hal(struct gk20a *g)
nvgpu_set_errata(g, NVGPU_ERRATA_200391931, true);
nvgpu_set_errata(g, NVGPU_ERRATA_SYNCPT_INVALID_ID_0, true);
nvgpu_set_errata(g, NVGPU_ERRATA_3524791, true);
nvgpu_set_errata(g, NVGPU_ERRATA_200075440, true);
nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -459,6 +459,7 @@ static const struct gops_gr_config tu104_ops_gr_config = {
.get_tpc_count_in_gpc = gm20b_gr_config_get_tpc_count_in_gpc,
.get_pes_tpc_mask = gm20b_gr_config_get_pes_tpc_mask,
.get_gpc_pes_mask = gv11b_gr_config_get_gpc_pes_mask,
.set_live_pes_mask = gv11b_gr_config_set_live_pes_mask,
.get_pd_dist_skip_table_size = gm20b_gr_config_get_pd_dist_skip_table_size,
.init_sm_id_table = gv100_gr_config_init_sm_id_table,
#ifdef CONFIG_NVGPU_GRAPHICS
@@ -1786,6 +1787,7 @@ int tu104_init_hal(struct gk20a *g)
nvgpu_set_errata(g, NVGPU_ERRATA_200391931, true);
nvgpu_set_errata(g, NVGPU_ERRATA_SYNCPT_INVALID_ID_0, true);
nvgpu_set_errata(g, NVGPU_ERRATA_3524791, true);
nvgpu_set_errata(g, NVGPU_ERRATA_200075440, true);
nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);

2
drivers/gpu/nvgpu/include/nvgpu/errata.h
View File

@@ -70,6 +70,8 @@ struct gk20a;
DEFINE_ERRATA(NVGPU_ERRATA_3288192, "GA10B", "L4 SCF NOT SUPPORTED"), \
/* NvGPU Driver */ \
DEFINE_ERRATA(NVGPU_ERRATA_SYNCPT_INVALID_ID_0, "SW", "Syncpt ID"),\
/* GV11B+ */ \
DEFINE_ERRATA(NVGPU_ERRATA_200075440, "GV11B", "PES MASK"),\
DEFINE_ERRATA(NVGPU_MAX_ERRATA_BITS, "NA", "Marks max number of flags"),
/**

2
drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
View File

@@ -944,6 +944,8 @@ struct gops_gr_config {
u32 (*get_gpc_pes_mask)(struct gk20a *g,
struct nvgpu_gr_config *config,
u32 gpc_index);
void (*set_live_pes_mask)(struct gk20a *g,
u32 gpc_count);
u32 (*get_gpc_rop_mask)(struct gk20a *g,
struct nvgpu_gr_config *config,
u32 gpc_index);

5
drivers/gpu/nvgpu/include/nvgpu/gr/config.h
View File

@@ -34,6 +34,11 @@ struct gk20a;
struct nvgpu_sm_info;
struct nvgpu_gr_config;
/*
* Number of bits represents a PES Mask.
*/
#define NUMBER_OF_BITS_COMPUTE_PES_MASK 4U
/**
* @brief Initialize GR engine configuration information.
*

4
drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_gr_ga100.h
View File

@@ -776,6 +776,10 @@
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U)
#define gr_gpc0_swdx_pes_mask_r() (0x005001d0U)
#define gr_gpc0_gpm_pd_live_physical_pes_r() (0x00500c50U)
#define gr_gpc0_gpm_pd_live_physical_pes_gpc0_gpm_pd_live_physical_pes_mask_f(v)\
((U32(v) & 0xfU) << 0U)
#define gr_gpcs_tpcs_tex_m_dbg2_r() (0x00419a3cU)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\

4
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h
View File

@@ -732,6 +732,10 @@
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\
((U32(v) & 0x3fffffU) << 0U)
#define gr_gpc0_swdx_pes_mask_r() (0x005001d0U)
#define gr_gpc0_gpm_pd_live_physical_pes_r() (0x00500c50U)
#define gr_gpc0_gpm_pd_live_physical_pes_gpc0_gpm_pd_live_physical_pes_mask_f(v)\
((U32(v) & 0xfU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419e00U)
#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v)\
((U32(v) & 0xffffffffU) << 0U)

4
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
View File

@@ -1107,6 +1107,10 @@
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\
((U32(v) & 0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000800U)
#define gr_gpc0_swdx_pes_mask_r() (0x005001d0U)
#define gr_gpc0_gpm_pd_live_physical_pes_r() (0x00500c50U)
#define gr_gpc0_gpm_pd_live_physical_pes_gpc0_gpm_pd_live_physical_pes_mask_f(v)\
((U32(v) & 0xfU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419e00U)
#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v)\
((U32(v) & 0xffffffffU) << 0U)

6
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_gr_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -829,6 +829,10 @@
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\
((U32(v) & 0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000700U)
#define gr_gpc0_swdx_pes_mask_r() (0x005001d0U)
#define gr_gpc0_gpm_pd_live_physical_pes_r() (0x00500c50U)
#define gr_gpc0_gpm_pd_live_physical_pes_gpc0_gpm_pd_live_physical_pes_mask_f(v)\
((U32(v) & 0xfU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419e00U)
#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v)\
((U32(v) & 0xffffffffU) << 0U)