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gpu: nvgpu: Add gr runlist support for MIG device

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This CL covers the following code changes,
1) Added api to validate the gr runlist for each gpu instance.
2) Added api to get the default gr runlist_id for each gpu instance.

JIRA NVGPU-5662
JIRA NVGPU-5663

Change-Id: Ib571d95740916799638c538cfd3d64abeb4dc636
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413808
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Lakshmanan M
2020-09-15 15:50:54 +05:30
committed by Alex Waterman
parent 235492ec25
commit 689cf24256
2 changed files with 62 additions and 2 deletions
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58
drivers/gpu/nvgpu/common/grmgr/grmgr.c
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@@ -302,7 +302,8 @@ u32 nvgpu_grmgr_get_gr_num_gpcs(struct gk20a *g, u32 gr_instance_id)
return gr_syspipe->num_gpc;
}
u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id, u32 gpc_local_id)
u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id,
u32 gpc_local_id)
{
struct nvgpu_gpu_instance *gpu_instance;
struct nvgpu_gr_syspipe *gr_syspipe;
@@ -340,3 +341,58 @@ u32 nvgpu_grmgr_get_gr_instance_id(struct gk20a *g, u32 gpu_instance_id)
return gr_instance_id;
}
bool nvgpu_grmgr_is_valid_runlist_id(struct gk20a *g,
u32 gpu_instance_id, u32 runlist_id)
{
if (gpu_instance_id < g->mig.num_gpu_instances) {
struct nvgpu_gpu_instance *gpu_instance =
&g->mig.gpu_instance[gpu_instance_id];
struct nvgpu_gr_syspipe *gr_syspipe =
&gpu_instance->gr_syspipe;
const struct nvgpu_device *gr_dev = gr_syspipe->gr_dev;
u32 id;
if (gr_dev->runlist_id == runlist_id) {
nvgpu_log(g, gpu_dbg_mig, "gr runlist found[%u]",
runlist_id);
return true;
}
for (id = 0U; id < gpu_instance->num_lce; id++) {
const struct nvgpu_device *lce_dev =
gpu_instance->lce_devs[id];
if (lce_dev->runlist_id == runlist_id) {
nvgpu_log(g, gpu_dbg_mig,
"lce/ce runlist found[%u]",
runlist_id);
return true;
}
}
}
nvgpu_err(g,
"gpu_instance_id[%u] >= num_gpu_instances[%u]",
gpu_instance_id, g->mig.num_gpu_instances);
return false;
}
u32 nvgpu_grmgr_get_gr_runlist_id(struct gk20a *g, u32 gpu_instance_id)
{
if (gpu_instance_id < g->mig.num_gpu_instances) {
struct nvgpu_gpu_instance *gpu_instance =
&g->mig.gpu_instance[gpu_instance_id];
struct nvgpu_gr_syspipe *gr_syspipe =
&gpu_instance->gr_syspipe;
const struct nvgpu_device *gr_dev = gr_syspipe->gr_dev;
return gr_dev->runlist_id;
}
nvgpu_err(g,
"gpu_instance_id[%u] >= num_gpu_instances[%u]",
gpu_instance_id, g->mig.num_gpu_instances);
return U32_MAX;
}