diff --git a/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h b/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h
index f63f49075..0232efb90 100644
--- a/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h
+++ b/drivers/gpu/nvgpu/common/gr/gr_falcon_priv.h
@@ -85,6 +85,35 @@ enum wait_ucode_status {
 /** Mailbox value in case of successful operation. */
 #define FALCON_UCODE_HANDSHAKE_INIT_COMPLETE	1U
 
+struct fecs_mthd_op_method {
+	/** Method address to send to FECS microcontroller. */
+	u32 addr;
+	/** Method data to send to FECS microcontroller. */
+	u32 data;
+};
+
+struct fecs_mthd_op_mailbox {
+	/** Mailbox ID to perform operation. */
+	u32 id;
+	/** Mailbox data to be written. */
+	u32 data;
+	/** Mailbox clear value. */
+	u32 clr;
+	/** Last read mailbox value. */
+	u32 *ret;
+	/** Mailbox value in case of operation success. */
+	u32 ok;
+	/** Mailbox value in case of operation failure. */
+	u32 fail;
+};
+
+struct fecs_mthd_op_cond {
+	/** Operation success condition. */
+	u32 ok;
+	/** Operation fail condition. */
+	u32 fail;
+};
+
 /**
  * FECS method operation structure.
  *
@@ -92,34 +121,12 @@ enum wait_ucode_status {
  * microcontroller.
  */
 struct nvgpu_fecs_method_op {
-	struct {
-		/** Method address to send to FECS microcontroller. */
-		u32 addr;
-		/** Method data to send to FECS microcontroller. */
-		u32 data;
-	} method;
-
-	struct {
-		/** Mailbox ID to perform operation. */
-		u32 id;
-		/** Mailbox data to be written. */
-		u32 data;
-		/** Mailbox clear value. */
-		u32 clr;
-		/** Last read mailbox value. */
-		u32 *ret;
-		/** Mailbox value in case of operation success. */
-		u32 ok;
-		/** Mailbox value in case of operation failure. */
-		u32 fail;
-	} mailbox;
-
-	struct {
-		/** Operation success condition. */
-		u32 ok;
-		/** Operation fail condition. */
-		u32 fail;
-	} cond;
+	/** Method struct */
+	struct fecs_mthd_op_method method;
+	/** Mailbox struct */
+	struct fecs_mthd_op_mailbox mailbox;
+	/** Condition struct */
+	struct fecs_mthd_op_cond cond;
 };
 
 /**
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h
index f721fd2d0..356b8e48e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gr/gr_falcon.h
@@ -138,19 +138,19 @@ struct nvgpu_fecs_host_intr_status {
  * Book keeping for ECC errors originating from FECS.
  */
 struct nvgpu_fecs_ecc_status {
-	/* This flag is set if IMEM corrected error is hit. */
+	/** This flag is set if IMEM corrected error is hit. */
 	bool imem_corrected_err;
-	/* This flag is set if IMEM uncorrected error is hit. */
+	/** This flag is set if IMEM uncorrected error is hit. */
 	bool imem_uncorrected_err;
-	/* This flag is set if DMEM corrected error is hit. */
+	/** This flag is set if DMEM corrected error is hit. */
 	bool dmem_corrected_err;
-	/* This flag is set if DMEM uncorrected error is hit. */
+	/** This flag is set if DMEM uncorrected error is hit. */
 	bool dmem_uncorrected_err;
-	/* Address of memory where ECC error occurred. */
+	/** Address of memory where ECC error occurred. */
 	u32  ecc_addr;
-	/* Number of corrected ECC errors. */
+	/** Number of corrected ECC errors. */
 	u32  corrected_delta;
-	/* Number of uncorrected ECC errors. */
+	/** Number of uncorrected ECC errors. */
 	u32  uncorrected_delta;
 };