From 692841ca56fb663b1945bd4a8f254bae579989ec Mon Sep 17 00:00:00 2001 From: Sai Nikhil Date: Fri, 26 Oct 2018 16:33:26 +0530 Subject: [PATCH] gpu: nvgpu: BIOS_GET_FIELD changes The BIOS_GET_FIELD() macro does a simple bit mask and shift operation. The value of this macro is assigned to variables of different data types. Casting the macro to different data types causes MISRA rule 10.8 violations. This issue is resolved by doing the cast inside the macro and returning the value in the correct data type. These changes also clear MISRA rule 10.1, 10.3 and 10.4 violations. JIRA NVGPU-992 JIRA NVGPU-1006 JIRA NVGPU-1010 Change-Id: I16345865d107f0ff0b34daa8b17d7d576eafcfbf Signed-off-by: Sai Nikhil Reviewed-on: https://git-master.nvidia.com/r/1936357 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk_domain.c | 156 +++-- drivers/gpu/nvgpu/clk/clk_fll.c | 14 +- drivers/gpu/nvgpu/clk/clk_freq_controller.c | 36 +- drivers/gpu/nvgpu/clk/clk_prog.c | 45 +- drivers/gpu/nvgpu/clk/clk_vin.c | 24 +- drivers/gpu/nvgpu/common/vbios/bios.c | 2 +- drivers/gpu/nvgpu/gp106/mclk_gp106.c | 5 +- drivers/gpu/nvgpu/include/nvgpu/bios.h | 611 +++++++++--------- .../gpu/nvgpu/include/nvgpu/posix/bitops.h | 9 +- drivers/gpu/nvgpu/lpwr/lpwr.c | 16 +- drivers/gpu/nvgpu/pmgr/pwrdev.c | 26 +- drivers/gpu/nvgpu/pmgr/pwrmonitor.c | 11 +- drivers/gpu/nvgpu/pmgr/pwrpolicy.c | 33 +- drivers/gpu/nvgpu/pmu_perf/vfe_equ.c | 28 +- drivers/gpu/nvgpu/pmu_perf/vfe_var.c | 49 +- drivers/gpu/nvgpu/pstate/pstate.c | 6 +- drivers/gpu/nvgpu/volt/volt_dev.c | 32 +- drivers/gpu/nvgpu/volt/volt_policy.c | 30 +- 18 files changed, 602 insertions(+), 531 deletions(-) diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index a15f05354..2ba457b0c 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c @@ -342,6 +342,7 @@ static int devinit_get_clocks_table_35(struct gk20a *g, struct vbios_clocks_table_1x_hal_clock_entry *vbiosclktbl1xhalentry; u8 *clocks_tbl_entry_ptr = NULL; u32 index = 0; + bool done = false; struct clk_domain *pclkdomain_dev; union { struct boardobj boardobj; @@ -405,13 +406,13 @@ static int devinit_get_clocks_table_35(struct gk20a *g, clk_domain_data.v3x.b_noise_aware_capable = vbiosclktbl1xhalentry[index].b_noise_aware_capable; - switch (BIOS_GET_FIELD(clocks_table_entry.flags0, + switch (BIOS_GET_FIELD(u32, clocks_table_entry.flags0, NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE)) { case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED: { clk_domain_data.boardobj.type = CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED; - clk_domain_data.v3x_fixed.freq_mhz = (u16)BIOS_GET_FIELD( + clk_domain_data.v3x_fixed.freq_mhz = BIOS_GET_FIELD(u16, clocks_table_entry.param1, NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ); break; @@ -422,18 +423,19 @@ static int devinit_get_clocks_table_35(struct gk20a *g, clk_domain_data.boardobj.type = CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER; clk_domain_data.v35_prog.super.clk_prog_idx_first = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param0, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST)); + BIOS_GET_FIELD(u8, clocks_table_entry.param0, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST); clk_domain_data.v35_prog.super.clk_prog_idx_last = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param0, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST)); + BIOS_GET_FIELD(u8, clocks_table_entry.param0, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST); clk_domain_data.v35_prog.super.noise_unaware_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX)); + BIOS_GET_FIELD(u8, clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX); if (clk_domain_data.v3x.b_noise_aware_capable) { clk_domain_data.v35_prog.super.b_force_noise_unaware_ordering = - (bool)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING)); + BIOS_GET_FIELD(bool, + clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING); } else { clk_domain_data.v35_prog.super.noise_aware_ordering_index = @@ -441,23 +443,23 @@ static int devinit_get_clocks_table_35(struct gk20a *g, clk_domain_data.v35_prog.super.b_force_noise_unaware_ordering = false; } clk_domain_data.v35_prog.pre_volt_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX)); + BIOS_GET_FIELD(u8, clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX); clk_domain_data.v35_prog.post_volt_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX)); + BIOS_GET_FIELD(u8, clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX); clk_domain_data.v35_prog.super.factory_delta.data.delta_khz = 0; clk_domain_data.v35_prog.super.factory_delta.type = 0; clk_domain_data.v35_prog.super.freq_delta_min_mhz = - (u16)(BIOS_GET_FIELD(clocks_table_entry.param1, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ)); + BIOS_GET_FIELD(s16, clocks_table_entry.param1, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ); clk_domain_data.v35_prog.super.freq_delta_max_mhz = - (u16)(BIOS_GET_FIELD(clocks_table_entry.param1, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ)); + BIOS_GET_FIELD(s16, clocks_table_entry.param1, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ); clk_domain_data.v35_prog.clk_vf_curve_count = vbiosclktbl1xhalentry[index].clk_vf_curve_count; break; @@ -468,19 +470,20 @@ static int devinit_get_clocks_table_35(struct gk20a *g, clk_domain_data.boardobj.type = CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE; clk_domain_data.v35_prog.super.clk_prog_idx_first = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param0, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST)); + BIOS_GET_FIELD(u8, clocks_table_entry.param0, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST); clk_domain_data.v35_prog.super.clk_prog_idx_last = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param0, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST)); + BIOS_GET_FIELD(u8, clocks_table_entry.param0, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST); clk_domain_data.v35_prog.super.noise_unaware_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX)); + BIOS_GET_FIELD(u8, clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX); if (clk_domain_data.v3x.b_noise_aware_capable) { clk_domain_data.v35_prog.super.b_force_noise_unaware_ordering = - (bool)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING)); + BIOS_GET_FIELD(bool, + clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING); } else { clk_domain_data.v35_prog.super.noise_aware_ordering_index = @@ -488,20 +491,20 @@ static int devinit_get_clocks_table_35(struct gk20a *g, clk_domain_data.v35_prog.super.b_force_noise_unaware_ordering = false; } clk_domain_data.v35_prog.pre_volt_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX)); + BIOS_GET_FIELD(u8, clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX); clk_domain_data.v35_prog.post_volt_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX)); + BIOS_GET_FIELD(u8, clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX); clk_domain_data.v35_prog.super.factory_delta.data.delta_khz = 0; clk_domain_data.v35_prog.super.factory_delta.type = 0; clk_domain_data.v35_prog.super.freq_delta_min_mhz = 0; clk_domain_data.v35_prog.super.freq_delta_max_mhz = 0; clk_domain_data.v35_slave.slave.master_idx = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param1, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN)); + BIOS_GET_FIELD(u8, clocks_table_entry.param1, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN); break; } @@ -510,10 +513,22 @@ static int devinit_get_clocks_table_35(struct gk20a *g, nvgpu_err(g, "error reading clock domain entry %d", index); status = -EINVAL; - goto done; + done = true; + break; } } + /* + * Previously we were doing "goto done" from the default case of + * the switch-case block above. MISRA however, gets upset about + * this because it wants a break statement in the default case. + * That's why we had to move the goto statement outside of the + * switch-case block. + */ + if(done) { + goto done; + } + pclkdomain_dev = construct_clk_domain(g, (void *)&clk_domain_data); if (pclkdomain_dev == NULL) { @@ -550,6 +565,7 @@ static int devinit_get_clocks_table_1x(struct gk20a *g, u8 *clocks_tbl_entry_ptr = NULL; u32 index = 0; struct clk_domain *pclkdomain_dev; + bool done = false; union { struct boardobj boardobj; struct clk_domain clk_domain; @@ -612,13 +628,13 @@ static int devinit_get_clocks_table_1x(struct gk20a *g, clk_domain_data.v3x.b_noise_aware_capable = vbiosclktbl1xhalentry[index].b_noise_aware_capable; - switch (BIOS_GET_FIELD(clocks_table_entry.flags0, + switch (BIOS_GET_FIELD(u32, clocks_table_entry.flags0, NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE)) { case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED: { clk_domain_data.boardobj.type = CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED; - clk_domain_data.v3x_fixed.freq_mhz = (u16)BIOS_GET_FIELD( + clk_domain_data.v3x_fixed.freq_mhz = BIOS_GET_FIELD(u16, clocks_table_entry.param1, NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ); break; @@ -629,21 +645,23 @@ static int devinit_get_clocks_table_1x(struct gk20a *g, clk_domain_data.boardobj.type = CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER; clk_domain_data.v3x_prog.clk_prog_idx_first = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param0, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST)); + BIOS_GET_FIELD(u8, clocks_table_entry.param0, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST); clk_domain_data.v3x_prog.clk_prog_idx_last = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param0, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST)); + BIOS_GET_FIELD(u8, clocks_table_entry.param0, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST); clk_domain_data.v3x_prog.noise_unaware_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX)); + BIOS_GET_FIELD(u8, clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX); if (clk_domain_data.v3x.b_noise_aware_capable) { clk_domain_data.v3x_prog.noise_aware_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX)); + BIOS_GET_FIELD(u8, + clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX); clk_domain_data.v3x_prog.b_force_noise_unaware_ordering = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING)); + BIOS_GET_FIELD(bool, + clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING); } else { clk_domain_data.v3x_prog.noise_aware_ordering_index = CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID; @@ -654,12 +672,12 @@ static int devinit_get_clocks_table_1x(struct gk20a *g, clk_domain_data.v3x_prog.factory_delta.type = 0; clk_domain_data.v3x_prog.freq_delta_min_mhz = - (u16)(BIOS_GET_FIELD(clocks_table_entry.param1, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ)); + BIOS_GET_FIELD(s16, clocks_table_entry.param1, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ); clk_domain_data.v3x_prog.freq_delta_max_mhz = - (u16)(BIOS_GET_FIELD(clocks_table_entry.param1, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ)); + BIOS_GET_FIELD(s16, clocks_table_entry.param1, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ); break; } @@ -668,22 +686,24 @@ static int devinit_get_clocks_table_1x(struct gk20a *g, clk_domain_data.boardobj.type = CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE; clk_domain_data.v3x_prog.clk_prog_idx_first = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param0, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST)); + BIOS_GET_FIELD(u8, clocks_table_entry.param0, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST); clk_domain_data.v3x_prog.clk_prog_idx_last = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param0, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST)); + BIOS_GET_FIELD(u8, clocks_table_entry.param0, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST); clk_domain_data.v3x_prog.noise_unaware_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX)); + BIOS_GET_FIELD(u8, clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX); if (clk_domain_data.v3x.b_noise_aware_capable) { clk_domain_data.v3x_prog.noise_aware_ordering_index = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX)); + BIOS_GET_FIELD(u8, + clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX); clk_domain_data.v3x_prog.b_force_noise_unaware_ordering = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING)); + BIOS_GET_FIELD(bool, + clocks_table_entry.param2, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING); } else { clk_domain_data.v3x_prog.noise_aware_ordering_index = CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID; @@ -694,8 +714,8 @@ static int devinit_get_clocks_table_1x(struct gk20a *g, clk_domain_data.v3x_prog.freq_delta_min_mhz = 0; clk_domain_data.v3x_prog.freq_delta_max_mhz = 0; clk_domain_data.v3x_slave.master_idx = - (u8)(BIOS_GET_FIELD(clocks_table_entry.param1, - NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN)); + BIOS_GET_FIELD(u8, clocks_table_entry.param1, + NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN); break; } @@ -704,10 +724,22 @@ static int devinit_get_clocks_table_1x(struct gk20a *g, nvgpu_err(g, "error reading clock domain entry %d", index); status = (u32) -EINVAL; - goto done; + done = true; + break; } } + /* + * Previously we were doing "goto done" from the default case of + * the switch-case block above. MISRA however, gets upset about + * this because it wants a break statement in the default case. + * That's why we had to move the goto statement outside of the + * switch-case block. + */ + if(done) { + goto done; + } + pclkdomain_dev = construct_clk_domain(g, (void *)&clk_domain_data); if (pclkdomain_dev == NULL) { diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index 487831581..8231348a9 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c @@ -302,8 +302,8 @@ static int devinit_get_fll_device_table(struct gk20a *g, } fll_dev_data.lut_device.vselect_mode = - (u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params, - NV_FLL_DESC_LUT_PARAMS_VSELECT); + BIOS_GET_FIELD(u8, fll_desc_table_entry.lut_params, + NV_FLL_DESC_LUT_PARAMS_VSELECT); if ( (u8)fll_desc_table_entry.vin_idx_sram != CTRL_CLK_VIN_ID_UNDEFINED) { pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, @@ -323,9 +323,9 @@ static int devinit_get_fll_device_table(struct gk20a *g, fll_dev_data.super.type = (u8)fll_desc_table_entry.fll_device_type; fll_dev_data.id = (u8)fll_desc_table_entry.fll_device_id; - fll_dev_data.mdiv = (u8)BIOS_GET_FIELD( + fll_dev_data.mdiv = BIOS_GET_FIELD(u8, fll_desc_table_entry.fll_params, - NV_FLL_DESC_FLL_PARAMS_MDIV); + NV_FLL_DESC_FLL_PARAMS_MDIV); fll_dev_data.input_freq_mhz = (u16)fll_desc_table_entry.ref_freq_mhz; fll_dev_data.min_freq_vfe_idx = @@ -343,11 +343,11 @@ static int devinit_get_fll_device_table(struct gk20a *g, fll_dev_data.vin_idx_sram = (u8)fll_desc_table_entry.vin_idx_sram; fll_dev_data.b_skip_pldiv_below_dvco_min = - (bool)BIOS_GET_FIELD(fll_desc_table_entry.fll_params, + BIOS_GET_FIELD(bool, fll_desc_table_entry.fll_params, NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN); fll_dev_data.lut_device.hysteresis_threshold = - (u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params, - NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD); + BIOS_GET_FIELD(u16, fll_desc_table_entry.lut_params, + NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD); fll_dev_data.regime_desc.regime_id = CTRL_CLK_FLL_REGIME_ID_FFR; fll_dev_data.regime_desc.fixed_freq_regime_limit_mhz = diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index b61f10295..a448e5eb5 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c @@ -228,16 +228,16 @@ static int clk_get_freq_controller_table(struct gk20a *g, nvgpu_memcpy((u8 *)&entry, entry_offset, sizeof(struct vbios_fct_1x_entry)); - if (!BIOS_GET_FIELD(entry.flags0, + if (!BIOS_GET_FIELD(bool, entry.flags0, NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE)) { continue; } - freq_controller_data.board_obj.type = (u8)BIOS_GET_FIELD( + freq_controller_data.board_obj.type = BIOS_GET_FIELD(u8, entry.flags0, NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE); ptmp_freq_cntr->controller_id = - (u8)BIOS_GET_FIELD(entry.param0, + BIOS_GET_FIELD(u8, entry.param0, NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID); pclk_domain = CLK_CLK_DOMAIN_GET((g->clk_pmu), @@ -246,51 +246,51 @@ static int clk_get_freq_controller_table(struct gk20a *g, pclk_domain->api_domain; ptmp_freq_cntr->parts_freq_mode = - (u8)BIOS_GET_FIELD(entry.param0, + BIOS_GET_FIELD(u8, entry.param0, NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE); /* Populate PI specific data */ ptmp_freq_cntr_pi->slowdown_pct_min = - (u8)BIOS_GET_FIELD(entry.param1, + BIOS_GET_FIELD(u8, entry.param1, NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN); ptmp_freq_cntr_pi->bpoison = - BIOS_GET_FIELD(entry.param1, + BIOS_GET_FIELD(bool, entry.param1, NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON); ptmp_freq_cntr_pi->prop_gain = - (s32)BIOS_GET_FIELD(entry.param2, + BIOS_GET_FIELD(s32, entry.param2, NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN); ptmp_freq_cntr_pi->integ_gain = - (s32)BIOS_GET_FIELD(entry.param3, + BIOS_GET_FIELD(s32, entry.param3, NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN); ptmp_freq_cntr_pi->integ_decay = - (s32)BIOS_GET_FIELD(entry.param4, + BIOS_GET_FIELD(s32, entry.param4, NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY); ptmp_freq_cntr_pi->volt_delta_min = - (s32)BIOS_GET_FIELD(entry.param5, - NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN); + BIOS_GET_FIELD(s32, entry.param5, + NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN); ptmp_freq_cntr_pi->volt_delta_max = - (s32)BIOS_GET_FIELD(entry.param6, - NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX); + BIOS_GET_FIELD(s32, entry.param6, + NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX); ptmp_freq_cntr->freq_cap_noise_unaware_vmin_above = - (s16)BIOS_GET_FIELD(entry.param7, + BIOS_GET_FIELD(s16, entry.param7, NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF); ptmp_freq_cntr->freq_cap_noise_unaware_vmin_below = - (s16)BIOS_GET_FIELD(entry.param7, - NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN); + BIOS_GET_FIELD(s16, entry.param7, + NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN); ptmp_freq_cntr->freq_hyst_pos_mhz = - (s16)BIOS_GET_FIELD(entry.param8, + BIOS_GET_FIELD(s16, entry.param8, NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS); ptmp_freq_cntr->freq_hyst_neg_mhz = - (s16)BIOS_GET_FIELD(entry.param8, + BIOS_GET_FIELD(s16, entry.param8, NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG); if (ptmp_freq_cntr_pi->volt_delta_max < diff --git a/drivers/gpu/nvgpu/clk/clk_prog.c b/drivers/gpu/nvgpu/clk/clk_prog.c index bf74cdd2e..4b9bb24b4 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/clk/clk_prog.c @@ -287,7 +287,7 @@ static int devinit_get_clk_prog_table_35(struct gk20a *g, sizeof(struct ctrl_clk_clk_prog_1x_master_table_slave_entry) * CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES); - prog_type = (u8)BIOS_GET_FIELD((prog.flags0), + prog_type = BIOS_GET_FIELD(u8, prog.flags0, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE); nvgpu_log_info(g, "Prog_type (master, slave type): 0x%x", prog_type); @@ -296,7 +296,7 @@ static int devinit_get_clk_prog_table_35(struct gk20a *g, continue; } - src_type = (u8)BIOS_GET_FIELD(prog.flags0, + src_type = BIOS_GET_FIELD(u8, prog.flags0, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE); nvgpu_log_info(g, "source type: 0x%x", src_type); switch (src_type) { @@ -304,10 +304,10 @@ static int devinit_get_clk_prog_table_35(struct gk20a *g, nvgpu_log_info(g, "Source type is PLL"); prog_data.v1x.source = CTRL_CLK_PROG_1X_SOURCE_PLL; prog_data.v1x.source_data.pll.pll_idx = - (u8)BIOS_GET_FIELD(prog.param0, + BIOS_GET_FIELD(u8, prog.param0, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX); prog_data.v1x.source_data.pll.freq_step_size_mhz = - (u8)BIOS_GET_FIELD(prog.param1, + BIOS_GET_FIELD(u8, prog.param1, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE); nvgpu_log_info(g, "pll_index: 0x%x freq_step_size: %d", prog_data.v1x.source_data.pll.pll_idx, @@ -359,7 +359,8 @@ static int devinit_get_clk_prog_table_35(struct gk20a *g, voltrailsecvfentries[j].sec_vf_entries[k].vfe_idx = (u8)vfsecprog.sec_vfe_idx; if (prog_data.v1x.source == CTRL_CLK_PROG_1X_SOURCE_FLL) { - voltrailsecvfentries[j].sec_vf_entries[k].dvco_offset_vfe_idx = (u8)BIOS_GET_FIELD( + voltrailsecvfentries[j].sec_vf_entries[k].dvco_offset_vfe_idx = + BIOS_GET_FIELD(u8, vfsecprog.param0, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_35_SEC_VF_ENTRY_PARAM0_FLL_DVCO_OFFSET_VFE_IDX); } else { @@ -381,15 +382,17 @@ static int devinit_get_clk_prog_table_35(struct gk20a *g, if (prog_type == NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO) { ratioslaveentries[j].clk_dom_idx = (u8)slaveprog.clk_dom_idx; - ratioslaveentries[j].ratio = (u8) - BIOS_GET_FIELD(slaveprog.param0, - NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO); + ratioslaveentries[j].ratio = + BIOS_GET_FIELD(u8, + slaveprog.param0, + NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO); } else { tableslaveentries[j].clk_dom_idx = (u8)slaveprog.clk_dom_idx; tableslaveentries[j].freq_mhz = - (u16)BIOS_GET_FIELD(slaveprog.param0, - NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ); + BIOS_GET_FIELD(u16, + slaveprog.param0, + NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ); } slaveentry += slaveszfmt; } @@ -529,19 +532,19 @@ static int devinit_get_clk_prog_table_1x(struct gk20a *g, (void) memset(tableslaveentries, 0xFF, sizeof(struct ctrl_clk_clk_prog_1x_master_table_slave_entry) * CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES); - src_type = (u8)BIOS_GET_FIELD(prog.flags0, - NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE); - prog_type = (u8)BIOS_GET_FIELD(prog.flags0, + src_type = BIOS_GET_FIELD(u8, prog.flags0, + NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE); + prog_type = BIOS_GET_FIELD(u8, prog.flags0, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE); switch (src_type) { case NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL: prog_data.v1x.source = CTRL_CLK_PROG_1X_SOURCE_PLL; prog_data.v1x.source_data.pll.pll_idx = - (u8)BIOS_GET_FIELD(prog.param0, + BIOS_GET_FIELD(u8, prog.param0, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX); prog_data.v1x.source_data.pll.freq_step_size_mhz = - (u8)BIOS_GET_FIELD(prog.param1, + BIOS_GET_FIELD(u8, prog.param1, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE); break; @@ -577,7 +580,8 @@ static int devinit_get_clk_prog_table_1x(struct gk20a *g, vfentries[j].vfe_idx = (u8)vfprog.vfe_idx; if (CTRL_CLK_PROG_1X_SOURCE_FLL == prog_data.v1x.source) { - vfentries[j].gain_vfe_idx = (u8)BIOS_GET_FIELD( + vfentries[j].gain_vfe_idx = + BIOS_GET_FIELD(u8, vfprog.param0, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX); } else { @@ -595,15 +599,16 @@ static int devinit_get_clk_prog_table_1x(struct gk20a *g, if (prog_type == NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO) { ratioslaveentries[j].clk_dom_idx = (u8)slaveprog.clk_dom_idx; - ratioslaveentries[j].ratio = (u8) - BIOS_GET_FIELD(slaveprog.param0, + ratioslaveentries[j].ratio = + BIOS_GET_FIELD(u8, slaveprog.param0, NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO); } else { tableslaveentries[j].clk_dom_idx = (u8)slaveprog.clk_dom_idx; tableslaveentries[j].freq_mhz = - (u16)BIOS_GET_FIELD(slaveprog.param0, - NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ); + BIOS_GET_FIELD(u16, + slaveprog.param0, + NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ); } slaveentry += slaveszfmt; } diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c index 485355fe1..963799a7e 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/clk/clk_vin.c @@ -290,12 +290,12 @@ static int devinit_get_vin_device_table(struct gk20a *g, sizeof(struct vin_descriptor_header_10)); pvinobjs->calibration_rev_vbios = - BIOS_GET_FIELD(vin_desc_table_header.flags0, + BIOS_GET_FIELD(u8, vin_desc_table_header.flags0, NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION); pvinobjs->vin_is_disable_allowed = - BIOS_GET_FIELD(vin_desc_table_header.flags0, + BIOS_GET_FIELD(bool, vin_desc_table_header.flags0, NV_VIN_DESC_FLAGS0_DISABLE_CONTROL); - cal_type = BIOS_GET_FIELD(vin_desc_table_header.flags0, + cal_type = BIOS_GET_FIELD(u32, vin_desc_table_header.flags0, NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE); if (cal_type == 0U) { cal_type = CTRL_CLK_VIN_CAL_TYPE_V10; @@ -304,22 +304,22 @@ static int devinit_get_vin_device_table(struct gk20a *g, switch (cal_type) { case CTRL_CLK_VIN_CAL_TYPE_V10: /* VIN calibration slope: XX.YYY mV/code => XXYYY uV/code*/ - slope = ((BIOS_GET_FIELD(vin_desc_table_header.vin_cal, - NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER) * 1000)) + - ((BIOS_GET_FIELD(vin_desc_table_header.vin_cal, + slope = ((BIOS_GET_FIELD(u32, vin_desc_table_header.vin_cal, + NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER) * 1000U)) + + ((BIOS_GET_FIELD(u32, vin_desc_table_header.vin_cal, NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION))); /* VIN calibration intercept: ZZZ.W mV => ZZZW00 uV */ - intercept = ((BIOS_GET_FIELD(vin_desc_table_header.vin_cal, - NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER) * 1000)) + - ((BIOS_GET_FIELD(vin_desc_table_header.vin_cal, - NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION) * 100)); + intercept = ((BIOS_GET_FIELD(u32, vin_desc_table_header.vin_cal, + NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER) * 1000U)) + + ((BIOS_GET_FIELD(u32, vin_desc_table_header.vin_cal, + NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION) * 100U)); break; case CTRL_CLK_VIN_CAL_TYPE_V20: - offset = BIOS_GET_FIELD(vin_desc_table_header.vin_cal, + offset = BIOS_GET_FIELD(s8, vin_desc_table_header.vin_cal, NV_VIN_DESC_VIN_CAL_OFFSET); - gain = BIOS_GET_FIELD(vin_desc_table_header.vin_cal, + gain = BIOS_GET_FIELD(s8, vin_desc_table_header.vin_cal, NV_VIN_DESC_VIN_CAL_GAIN); break; default: diff --git a/drivers/gpu/nvgpu/common/vbios/bios.c b/drivers/gpu/nvgpu/common/vbios/bios.c index 609a6c540..b8672d693 100644 --- a/drivers/gpu/nvgpu/common/vbios/bios.c +++ b/drivers/gpu/nvgpu/common/vbios/bios.c @@ -492,7 +492,7 @@ int nvgpu_bios_get_lpwr_nvlink_table_hdr(struct gk20a *g) } g->nvlink.initpll_ordinal = - BIOS_GET_FIELD(hdr.line_rate_initpll_ordinal, + BIOS_GET_FIELD(u8, hdr.line_rate_initpll_ordinal, VBIOS_LPWR_NVLINK_TABLE_HDR_INITPLL_ORDINAL); nvgpu_log(g, gpu_dbg_nvlink, " Nvlink initpll_ordinal: 0x%x", g->nvlink.initpll_ordinal); diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c index d0b731b49..71aaaf84e 100644 --- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c @@ -3107,7 +3107,7 @@ static int mclk_get_memclk_table(struct gk20a *g) continue; } - script_index = BIOS_GET_FIELD(memclock_base_entry.flags1, + script_index = BIOS_GET_FIELD(u8, memclock_base_entry.flags1, VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX); script_ptr = nvgpu_bios_read_u32(g, @@ -3162,7 +3162,8 @@ static int mclk_get_memclk_table(struct gk20a *g) } - cmd_script_index = BIOS_GET_FIELD(memclock_base_entry.flags2, + cmd_script_index = BIOS_GET_FIELD(u8, + memclock_base_entry.flags2, VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX); cmd_script_ptr = nvgpu_bios_read_u32(g, diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 64922b92f..a51022bcc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h @@ -74,7 +74,14 @@ struct bit_token { u16 data_ptr; } __packed; -#define BIOS_GET_FIELD(value, name) (((value) & (name##_MASK)) >> (name##_SHIFT)) +/* + * BIOS_GET_FIELD returns the value of a given field 'name' of the param 'value' + * from VBIOS tables adjusted to the required 'type'. + */ +#define BIOS_GET_FIELD(type, value, name) ({\ + typeof(value) x = ((value) & (name##_MASK)) >> (name##_SHIFT); \ + (type)x; \ +}) struct fll_descriptor_header { u8 version; @@ -108,17 +115,17 @@ struct fll_descriptor_entry_10 { u16 ffr_cutoff_freq_mhz; } __packed; -#define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F -#define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 +#define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1FU +#define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0U -#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_MASK 0x20 -#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_SHIFT 5 +#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_MASK 0x20U +#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_SHIFT 5U -#define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 -#define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 +#define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3U +#define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0U -#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C -#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2 +#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3CU +#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2U struct vin_descriptor_header_10 { u8 version; @@ -135,32 +142,32 @@ struct vin_descriptor_entry_10 { u8 vin_device_id; } __packed; -#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7 -#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0 +#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7U +#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0U -#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_MASK 0xF0 -#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_SHIFT 4 +#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_MASK 0xF0U +#define NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE_SHIFT 4U -#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8 -#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3 +#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8U +#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3U -#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF -#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0 +#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FFU +#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0U -#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00 -#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT 10 +#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00U +#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT 10U -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000 -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14 +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000U +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14U -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000 -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18 +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000U +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18U -#define NV_VIN_DESC_VIN_CAL_OFFSET_MASK 0x7F -#define NV_VIN_DESC_VIN_CAL_OFFSET_SHIFT 0 +#define NV_VIN_DESC_VIN_CAL_OFFSET_MASK 0x7FU +#define NV_VIN_DESC_VIN_CAL_OFFSET_SHIFT 0U -#define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80 -#define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7 +#define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80U +#define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7U #define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07U struct vbios_clocks_table_1x_header { @@ -200,49 +207,49 @@ struct vbios_clocks_table_35_entry { u16 param3; } __packed; -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER 0x01 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE 0x02 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1FU +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER 0x01U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE 0x02U -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK 0xFF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK 0xFF00 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK 0xFFU +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT 0U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK 0xFF00U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08U -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK 0xFFFF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK 0xFFFFU +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT 0U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFFU +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0U -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0U -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK 0xF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK 0xFU +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT 0U -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xFU +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0U -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK 0xF0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT 4 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK 0xF0U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT 4U -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00U +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01U -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_MASK 0xF -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_MASK 0xFU +#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX_SHIFT 0U -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_MASK 0xF0 -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_SHIFT 4 +#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_MASK 0xF0U +#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX_SHIFT 4U -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_MASK 0xFF -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK 0xFF00 -#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08 +#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_MASK 0xFFU +#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MIN_SHIFT 0U +#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK 0xFF00U +#define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08U #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08U #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_VERSION 0x10U @@ -283,26 +290,26 @@ struct vbios_clock_programming_table_1x_entry { u32 rsvd1; } __packed; -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK 0x0FU -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT 0x00U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO 0x00U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE 0x01U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE 0x02U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_35_ENTRY_FLAGS0_TYPE_DISABLED 0x0FU +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK 0x0FU +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT 0x00U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO 0x00U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE 0x01U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE 0x02U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_35_ENTRY_FLAGS0_TYPE_DISABLED 0x0FU -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK 0x70U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT 0x04U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL 0x00U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE 0x01U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL 0x02U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK 0x70U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT 0x04U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL 0x00U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE 0x01U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL 0x02U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK 0x80U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT 0x07U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE 0x00U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE 0x01U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK 0x80U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT 0x07U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE 0x00U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE 0x01U -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK 0xFFU -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT 0x00U +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK 0xFFU +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT 0x00U #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFFU #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0x00U @@ -372,52 +379,52 @@ struct vbios_vfe_3x_var_entry_struct { #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05U #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFFU +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00U +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000U +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFFU +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00U +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000U +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000U +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_MASK 0x2000000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_SHIFT 25 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_MASK 0x2000000U +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_SHIFT 25U #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000U +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFFU +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00U +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFFU +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00U +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFFU +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFFU +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0U -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFFU +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0U #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17U #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18U @@ -444,45 +451,45 @@ struct vbios_vfe_3x_equ_entry_struct { #define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFFU -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFFU +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0U -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFFU +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0U -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8U -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16U #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000U #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001U -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFFU +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0U -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFFU +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0U -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFFU +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0U -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8U -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002U -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS 0x0 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ 0x1 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV 0x2 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xFU +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS 0x0U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ 0x1U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV 0x2U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3U +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4U #define NV_VFIELD_DESC_SIZE_BYTE 0x00000000U #define NV_VFIELD_DESC_SIZE_WORD 0x00000001U @@ -579,16 +586,16 @@ struct vbios_pstate_entry_5x { struct vbios_pstate_entry_clock_5x clockEntry[PERF_CLK_DOMAINS_IDX_MAX]; } __packed; -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_SHIFT 0 -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_MASK 0x00003FFF +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_SHIFT 0U +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_MASK 0x00003FFFU -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_SHIFT 0 -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_MASK 0x00003FFF +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_SHIFT 0U +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_MASK 0x00003FFFU -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14 -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000 +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14U +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000U -#define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFFU +#define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFFU #define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11U @@ -630,13 +637,11 @@ struct vbios_memory_clock_base_entry_11 { /* Script Pointer Index */ /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX 3:2*/ -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK \ - ((u8)0xc) -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT 2 +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK 0xcU +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT 2U /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX 1:0*/ -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK \ - ((u8)0x3) -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK 0x3U +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0U #define VBIOS_POWER_SENSORS_VERSION_2X 0x20U #define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008U @@ -660,32 +665,32 @@ struct pwr_sensors_2x_entry { u32 sensor_param3; } __packed; -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xFU +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0U #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001U -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_MASK 0x100 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_SHIFT 8 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFFU +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_MASK 0x100U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_SHIFT 8U -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_MASK 0xFFFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_SHIFT 16 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_MASK 0xFFFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_SHIFT 16 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_MASK 0xFFFFU +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_SHIFT 0U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_MASK 0xFFFF0000U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_SHIFT 16U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_MASK 0xFFFFU +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_SHIFT 0U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_MASK 0xFFFF0000U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_SHIFT 16U -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_MASK 0xFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_SHIFT 16 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_MASK 0xFFFFU +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_SHIFT 0U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_MASK 0xFF0000U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_SHIFT 16U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_MASK 0xFFFFU +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_SHIFT 0U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000U +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16U #define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20U #define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006U @@ -711,14 +716,14 @@ struct pwr_topology_2x_entry { u32 param2; } __packed; -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xFU +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0U #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR U8(0x00000001) -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFFU +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0U +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00U +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8U #define VBIOS_POWER_POLICY_VERSION_3X 0x30U #define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025U @@ -770,28 +775,28 @@ struct pwr_policy_3x_entry_struct { u32 filter_param; } __packed; -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xFU +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0U #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005U -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10U +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4U -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_MASK 0x1 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_SHIFT 0 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_MASK 0x2 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_SHIFT 1 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_MASK 0x3C -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_SHIFT 2 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_MASK 0x1U +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_SHIFT 0U +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_MASK 0x2U +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_SHIFT 1U +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_MASK 0x3CU +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_SHIFT 2U -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_MASK 0xFF -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_SHIFT 0 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_MASK 0xFF00 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_SHIFT 8 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_MASK 0x10000 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_SHIFT 16 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_MASK 0xFFU +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_SHIFT 0U +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_MASK 0xFF00U +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_SHIFT 8U +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_MASK 0x10000U +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_SHIFT 16U -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFFU +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0U /* Voltage Rail Table */ struct vbios_voltage_rail_table_1x_header { @@ -844,45 +849,45 @@ struct vbios_voltage_device_table_1x_entry { #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02U #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT 0 + U32(GENMASK(23, 0)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT 0U #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24 + U32(GENMASK(31, 24)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24U #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT 0 + U32(GENMASK(23, 0)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT 0U #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT 24 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00 + U32(GENMASK(31, 24)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT 24U +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00U #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \ - 0x01 + 0x01U #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \ - 0x02 + 0x02U #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_IPC_VMIN \ 0x03U #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0 + U32(GENMASK(23, 0)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0U #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT 24 + U32(GENMASK(31, 24)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT 24U #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT 0 + U32(GENMASK(23, 0)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT 0U #define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT 24 + U32(GENMASK(31, 24)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT 24U #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT 0 + U32(GENMASK(23, 0)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT 0U #define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT 24 + U32(GENMASK(31, 24)) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT 24U /* Voltage Policy Table */ struct vbios_voltage_policy_table_1x_header { @@ -908,39 +913,39 @@ struct vbios_voltage_policy_table_1x_entry { #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ - GENMASK(7, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0 -#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK GENMASK(8, 31) -#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT 8 + U32(GENMASK(7, 0)) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0U +#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK U32(GENMASK(8, 31)) +#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT 8U #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \ - GENMASK(7, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0 + U32(GENMASK(7, 0)) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0U #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \ - GENMASK(15, 8) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8 + U32(GENMASK(15, 8)) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8U #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \ - GENMASK(23, 16) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16 + U32(GENMASK(23, 16)) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16U #define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 + U32(GENMASK(31, 24)) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24U #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ - GENMASK(15, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT 0 + U32(GENMASK(15, 0)) +#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT 0U #define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_MASK \ - GENMASK(31, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_SHIFT 0 + U32(GENMASK(31, 0)) +#define NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV_SHIFT 0U #define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_MASK \ - GENMASK(31, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_SHIFT 0 + U32(GENMASK(31, 0)) +#define NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV_SHIFT 0U /* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ - GENMASK(15, 0) + U32(GENMASK(15, 0)) #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ - 0 + 0U #define VBIOS_THERM_DEVICE_VERSION_1X 0x10U @@ -960,14 +965,14 @@ struct therm_device_1x_entry { } ; #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID 0x00U -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01U +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01U #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC 0x02U #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI 0x03U #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE 0x70U #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED 0x71U -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0 +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFFU +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0U #define VBIOS_THERM_CHANNEL_VERSION_1X 0x10U @@ -995,11 +1000,11 @@ struct therm_channel_1x_entry { #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01U -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0 +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFFU +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0U -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFF -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0 +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFFU +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0U /* Frequency Controller Table */ struct vbios_fct_1x_header { @@ -1024,65 +1029,65 @@ struct vbios_fct_1x_entry { u32 param8; } __packed; -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK GENMASK(3, 0) -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0 -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI 0x1 +#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK U8(GENMASK(3, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0U +#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0U +#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI 0x1U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK GENMASK(7, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS 0x00 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC 0x01 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR 0x02 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0 0x03 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1 0x04 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2 0x05 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3 0x06 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4 0x07 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5 0x08 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS 0x09 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK U16(GENMASK(7, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS 0x00U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC 0x01U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR 0x02U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0 0x03U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1 0x04U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2 0x05U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3 0x06U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4 0x07U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5 0x08U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS 0x09U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK GENMASK(9, 8) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN 0x1 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX 0x2 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG 0x3 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK U16(GENMASK(9, 8)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN 0x1U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX 0x2U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG 0x3U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK GENMASK(7, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK U16(GENMASK(7, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK GENMASK(8, 8) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO 0x0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK U16(GENMASK(8, 8)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO 0x0U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK U32(GENMASK(31, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK U32(GENMASK(31, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK U32(GENMASK(31, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK U32(GENMASK(31, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK U32(GENMASK(31, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK GENMASK(15, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK GENMASK(31, 16) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK U32(GENMASK(15, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK U32(GENMASK(31, 16)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16U -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK GENMASK(15, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK U32(GENMASK(15, 0)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0U +#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK U32(GENMASK(31, 16)) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16U /* LPWR Index Table */ struct nvgpu_bios_lpwr_idx_table_1x_header { @@ -1117,15 +1122,15 @@ struct nvgpu_bios_lpwr_ms_table_1x_entry { u16 dynamic_current_sram; } __packed; -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_MASK GENMASK(0, 0) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SHIFT 0 -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_MASK GENMASK(2, 2) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_SHIFT 2 +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_MASK U32(GENMASK(0, 0)) +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SHIFT 0U +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_MASK U32(GENMASK(2, 2)) +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_SHIFT 2U #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_MASK \ - GENMASK(3, 3) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_SHIFT 3 -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_MASK GENMASK(5, 5) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_SHIFT 5 + U32(GENMASK(3, 3)) +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_SHIFT 3U +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_MASK U32(GENMASK(5, 5)) +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_SHIFT 5U /* LPWR GR Table */ struct nvgpu_bios_lpwr_gr_table_1x_header { @@ -1142,11 +1147,11 @@ struct nvgpu_bios_lpwr_gr_table_1x_entry { u32 feautre_mask; } __packed; -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_MASK GENMASK(0, 0) -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_SHIFT 0 +#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_MASK U32(GENMASK(0, 0)) +#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_SHIFT 0U -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 +#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK U32(GENMASK(4, 4)) +#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4U #define VBIOS_LPWR_NVLINK_TABLE_HDR_INITPLL_ORDINAL_MASK 0x07U #define VBIOS_LPWR_NVLINK_TABLE_HDR_INITPLL_ORDINAL_SHIFT 0x00U diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h index 95366ff71..44d555f83 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h +++ b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h @@ -29,17 +29,18 @@ * Assume an 8 bit byte, of course. */ #define BITS_PER_BYTE 8UL -#define BITS_PER_LONG (__SIZEOF_LONG__ * BITS_PER_BYTE) +#define BITS_PER_LONG ((unsigned long)__SIZEOF_LONG__ * BITS_PER_BYTE) #define BITS_TO_LONGS(bits) \ - ((bits) + (BITS_PER_LONG - 1) / BITS_PER_LONG) + ((bits) + (BITS_PER_LONG - 1UL) / BITS_PER_LONG) /* * Deprecated; use the explicit BITxx() macros instead. */ #define BIT(i) BIT64(i) -#define GENMASK(h, l) \ - (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#define GENMASK(hi, lo) \ + (((~0UL) - (1UL << (lo)) + 1UL) & \ + (~0UL >> (BITS_PER_LONG - 1UL - (unsigned long)(hi)))) #define DECLARE_BITMAP(bmap, bits) \ unsigned long bmap[BITS_TO_LONGS(bits)] diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c index 74271a16c..16ffb9164 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.c +++ b/drivers/gpu/nvgpu/lpwr/lpwr.c @@ -102,14 +102,14 @@ static int get_lpwr_gr_table(struct gk20a *g) nvgpu_memcpy((u8 *)&entry, entry_addr, sizeof(struct nvgpu_bios_lpwr_gr_table_1x_entry)); - if (BIOS_GET_FIELD(entry.feautre_mask, - NV_VBIOS_LPWR_MS_FEATURE_MASK_MS) != 0U) { + if (BIOS_GET_FIELD(bool, entry.feautre_mask, + NV_VBIOS_LPWR_MS_FEATURE_MASK_MS)) { pgr_data->entry[idx].gr_enabled = true; pgr_data->entry[idx].feature_mask = NVGPU_PMU_GR_FEATURE_MASK_ALL; - if (!BIOS_GET_FIELD(entry.feautre_mask, + if (!BIOS_GET_FIELD(bool, entry.feautre_mask, NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG)) { pgr_data->entry[idx].feature_mask &= ~NVGPU_PMU_GR_FEATURE_MASK_RPPG; @@ -156,26 +156,26 @@ static int get_lpwr_ms_table(struct gk20a *g) nvgpu_memcpy((u8 *)&entry, entry_addr, sizeof(struct nvgpu_bios_lpwr_ms_table_1x_entry)); - if (BIOS_GET_FIELD(entry.feautre_mask, - NV_VBIOS_LPWR_MS_FEATURE_MASK_MS) != 0U) { + if (BIOS_GET_FIELD(bool, entry.feautre_mask, + NV_VBIOS_LPWR_MS_FEATURE_MASK_MS)) { pms_data->entry[idx].ms_enabled = true; pms_data->entry[idx].feature_mask = NVGPU_PMU_MS_FEATURE_MASK_ALL; - if (!BIOS_GET_FIELD(entry.feautre_mask, + if (!BIOS_GET_FIELD(bool, entry.feautre_mask, NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING)) { pms_data->entry[idx].feature_mask &= ~NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING; } - if (!BIOS_GET_FIELD(entry.feautre_mask, + if (!BIOS_GET_FIELD(bool, entry.feautre_mask, NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR)) { pms_data->entry[idx].feature_mask &= ~NVGPU_PMU_MS_FEATURE_MASK_SW_ASR; } - if (!BIOS_GET_FIELD(entry.feautre_mask, + if (!BIOS_GET_FIELD(bool, entry.feautre_mask, NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG)) { pms_data->entry[idx].feature_mask &= ~NVGPU_PMU_MS_FEATURE_MASK_RPPG; diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c index 547edd153..c18b1881b 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrdev.c +++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c @@ -194,15 +194,14 @@ static int devinit_get_pwr_device_table(struct gk20a *g, (curr_pwr_device_table_ptr + 1), (VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 - 1U)); - device_type = (u8)BIOS_GET_FIELD( - pwr_sensor_table_entry.flags0, - NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS); + device_type = BIOS_GET_FIELD(u8, pwr_sensor_table_entry.flags0, + NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS); if (device_type == NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C) { - i2c_dev_idx = (u8)BIOS_GET_FIELD( + i2c_dev_idx = BIOS_GET_FIELD(u8, pwr_sensor_table_entry.class_param0, NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX); - use_fxp8_8 = (u8)BIOS_GET_FIELD( + use_fxp8_8 = BIOS_GET_FIELD(bool, pwr_sensor_table_entry.class_param0, NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8); @@ -211,41 +210,42 @@ static int devinit_get_pwr_device_table(struct gk20a *g, pwr_device_data.ina3221.r_shuntm_ohm[1].use_fxp8_8 = use_fxp8_8; pwr_device_data.ina3221.r_shuntm_ohm[2].use_fxp8_8 = use_fxp8_8; pwr_device_data.ina3221.r_shuntm_ohm[0].rshunt_value = - (u16)BIOS_GET_FIELD( + BIOS_GET_FIELD(u16, pwr_sensor_table_entry.sensor_param0, NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM); pwr_device_data.ina3221.r_shuntm_ohm[1].rshunt_value = - (u16)BIOS_GET_FIELD( + BIOS_GET_FIELD(u16, pwr_sensor_table_entry.sensor_param0, NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM); pwr_device_data.ina3221.r_shuntm_ohm[2].rshunt_value = - (u16)BIOS_GET_FIELD( + BIOS_GET_FIELD(u16, pwr_sensor_table_entry.sensor_param1, NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM); + pwr_device_data.ina3221.configuration = - (u16)BIOS_GET_FIELD( + BIOS_GET_FIELD(u16, pwr_sensor_table_entry.sensor_param1, NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION); pwr_device_data.ina3221.mask_enable = - (u16)BIOS_GET_FIELD( + BIOS_GET_FIELD(u16, pwr_sensor_table_entry.sensor_param2, NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE); pwr_device_data.ina3221.gpio_function = - (u8)BIOS_GET_FIELD( + BIOS_GET_FIELD(u8, pwr_sensor_table_entry.sensor_param2, NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION); pwr_device_data.ina3221.curr_correct_m = - (u16)BIOS_GET_FIELD( + BIOS_GET_FIELD(u16, pwr_sensor_table_entry.sensor_param3, NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M); pwr_device_data.ina3221.curr_correct_b = - (u16)BIOS_GET_FIELD( + BIOS_GET_FIELD(s16, pwr_sensor_table_entry.sensor_param3, NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B); diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c index 304038952..daea0ee36 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c +++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c @@ -244,15 +244,16 @@ static int devinit_get_pwr_topology_table(struct gk20a *g, (curr_pwr_topology_table_ptr + 2), (VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 - 2U)); - class_type = (u8)BIOS_GET_FIELD( - pwr_topology_table_entry.flags0, - NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS); + class_type = BIOS_GET_FIELD(u8, pwr_topology_table_entry.flags0, + NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS); if (class_type == NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR) { - pwr_topology_data.sensor.pwr_dev_idx = (u8)BIOS_GET_FIELD( + pwr_topology_data.sensor.pwr_dev_idx = + BIOS_GET_FIELD(u8, pwr_topology_table_entry.param1, NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX); - pwr_topology_data.sensor.pwr_dev_prov_idx = (u8)BIOS_GET_FIELD( + pwr_topology_data.sensor.pwr_dev_prov_idx = + BIOS_GET_FIELD(u8, pwr_topology_table_entry.param1, NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX); diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c index bbc486dff..ac6a82e5c 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c @@ -575,9 +575,8 @@ static int devinit_get_pwr_policy_table(struct gk20a *g, packed_entry = (struct pwr_policy_3x_entry_struct *)ptr; - class_type = (u8)BIOS_GET_FIELD( - packed_entry->flags0, - NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS); + class_type = BIOS_GET_FIELD(u8, packed_entry->flags0, + NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS); if (class_type != NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD) { continue; @@ -605,7 +604,7 @@ static int devinit_get_pwr_policy_table(struct gk20a *g, ppwrpolicyobjs->policy_idxs[5] = hdr.pwr_tgt_floor_policy_idx; ppwrpolicyobjs->policy_idxs[6] = hdr.sm_bus_policy_idx; - integral_control = (bool)BIOS_GET_FIELD(entry.flags1, + integral_control = BIOS_GET_FIELD(bool, entry.flags1, NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL); if (integral_control) { @@ -622,21 +621,21 @@ static int devinit_get_pwr_policy_table(struct gk20a *g, 0x0, sizeof( struct ctrl_pmgr_pwr_policy_info_integral)); } - pwr_policy_data.hw_threshold.threshold_idx = (u8) - BIOS_GET_FIELD(entry.param0, + pwr_policy_data.hw_threshold.threshold_idx = + BIOS_GET_FIELD(u8, entry.param0, NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX); pwr_policy_data.hw_threshold.b_use_low_threshold = - BIOS_GET_FIELD(entry.param0, + BIOS_GET_FIELD(bool, entry.param0, NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE); if (pwr_policy_data.hw_threshold.b_use_low_threshold) { - pwr_policy_data.hw_threshold.low_threshold_idx = (u8) - BIOS_GET_FIELD(entry.param0, + pwr_policy_data.hw_threshold.low_threshold_idx = + BIOS_GET_FIELD(u8, entry.param0, NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX); - pwr_policy_data.hw_threshold.low_threshold_value = (u16) - BIOS_GET_FIELD(entry.param1, + pwr_policy_data.hw_threshold.low_threshold_value = + BIOS_GET_FIELD(u16, entry.param1, NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL); } @@ -646,13 +645,13 @@ static int devinit_get_pwr_policy_table(struct gk20a *g, pwr_policy_data.boardobj.type = CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD; pwr_policy_data.pwrpolicy.ch_idx = entry.ch_idx; - pwr_policy_data.pwrpolicy.limit_unit = (u8) - BIOS_GET_FIELD(entry.flags0, - NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT); + pwr_policy_data.pwrpolicy.limit_unit = + BIOS_GET_FIELD(u8, entry.flags0, + NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT); pwr_policy_data.pwrpolicy.filter_type = - (enum ctrl_pmgr_pwr_policy_filter_type) - BIOS_GET_FIELD(entry.flags1, - NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE); + BIOS_GET_FIELD(enum ctrl_pmgr_pwr_policy_filter_type, + entry.flags1, + NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE); pwr_policy_data.pwrpolicy.limit_min = entry.limit_min; pwr_policy_data.pwrpolicy.limit_rated = entry.limit_rated; diff --git a/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c b/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c index fda544076..831f1998f 100644 --- a/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c +++ b/drivers/gpu/nvgpu/pmu_perf/vfe_equ.c @@ -148,6 +148,7 @@ static int devinit_get_vfe_equ_table(struct gk20a *g, struct vfe_equ *pequ; u8 equ_type = 0; u32 szfmt; + bool done = false; union { struct boardobj board_obj; struct vfe_equ super; @@ -208,7 +209,8 @@ static int devinit_get_vfe_equ_table(struct gk20a *g, equ_data.super.out_range_min = equ.out_range_min; equ_data.super.out_range_max = equ.out_range_max; - switch (BIOS_GET_FIELD(equ.param3, VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE)) { + switch (BIOS_GET_FIELD(u32, equ.param3, + VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE)) { case VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS: equ_data.super.output_type = CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UNITLESS; @@ -237,6 +239,17 @@ static int devinit_get_vfe_equ_table(struct gk20a *g, default: nvgpu_err(g, "unrecognized output id @vfeequ index %d", index); + done = true; + break; + } + /* + * Previously we were doing "goto done" from the default case of + * the switch-case block above. MISRA however, gets upset about + * this because it wants a break statement in the default case. + * That's why we had to move the goto statement outside of the + * switch-case block. + */ + if(done) { goto done; } @@ -256,21 +269,20 @@ static int devinit_get_vfe_equ_table(struct gk20a *g, case VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX: equ_type = CTRL_PERF_VFE_EQU_TYPE_MINMAX; - equ_data.minmax.b_max = BIOS_GET_FIELD(equ.param0, + equ_data.minmax.b_max = BIOS_GET_FIELD(bool, equ.param0, VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT) && (VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX != 0U); - equ_data.minmax.equ_idx0 = (u8)BIOS_GET_FIELD( + equ_data.minmax.equ_idx0 = BIOS_GET_FIELD(u8, equ.param0, VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0); - equ_data.minmax.equ_idx1 = (u8)BIOS_GET_FIELD( + equ_data.minmax.equ_idx1 = BIOS_GET_FIELD(u8, equ.param0, VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1); break; case VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE: { - u8 cmp_func = (u8)BIOS_GET_FIELD( - equ.param1, + u8 cmp_func = BIOS_GET_FIELD(u8, equ.param1, VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION); equ_type = CTRL_PERF_VFE_EQU_TYPE_COMPARE; @@ -295,10 +307,10 @@ static int devinit_get_vfe_equ_table(struct gk20a *g, status = -EINVAL; goto done; } - equ_data.compare.equ_idx_true = (u8)BIOS_GET_FIELD( + equ_data.compare.equ_idx_true = BIOS_GET_FIELD(u8, equ.param1, VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE); - equ_data.compare.equ_idx_false = (u8)BIOS_GET_FIELD( + equ_data.compare.equ_idx_false = BIOS_GET_FIELD(u8, equ.param1, VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE); equ_data.compare.criteria = equ.param0; diff --git a/drivers/gpu/nvgpu/pmu_perf/vfe_var.c b/drivers/gpu/nvgpu/pmu_perf/vfe_var.c index ea7094394..4e0ec62e1 100644 --- a/drivers/gpu/nvgpu/pmu_perf/vfe_var.c +++ b/drivers/gpu/nvgpu/pmu_perf/vfe_var.c @@ -897,7 +897,8 @@ static int devinit_get_vfe_var_table(struct gk20a *g, u32 index = 0; struct vfe_var *pvar; u8 var_type; - u32 szfmt; + u32 szfmt, val; + bool done = false; union { struct boardobj board_obj; struct vfe_var super; @@ -966,33 +967,35 @@ static int devinit_get_vfe_var_table(struct gk20a *g, var_type = CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP; var_data.single_sensed_temp.temp_default = 0x9600; var_data.single_sensed_temp.therm_channel_index = - (u8)BIOS_GET_FIELD(var.param0, - VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX); + BIOS_GET_FIELD(u8, var.param0, + VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX); + val = BIOS_GET_FIELD(u32, var.param0, + VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS) << 5U; var_data.single_sensed_temp.temp_hysteresis_positive = - (u8)BIOS_GET_FIELD(var.param0, - VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS) << 5; + (int)val; + val = BIOS_GET_FIELD(u32, var.param0, + VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG) << 5U; var_data.single_sensed_temp.temp_hysteresis_negative = - (u8)BIOS_GET_FIELD(var.param0, - VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG) << 5; + (int)val; break; case VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE: var_type = CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE; var_data.single_sensed_fuse.vfield_info.v_field_id = - (u8)BIOS_GET_FIELD(var.param0, + BIOS_GET_FIELD(u8, var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID); var_data.single_sensed_fuse.vfield_ver_info.v_field_id_ver = - (u8)BIOS_GET_FIELD(var.param0, + BIOS_GET_FIELD(u8, var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER); var_data.single_sensed_fuse.vfield_ver_info.ver_expected = - (u8)BIOS_GET_FIELD(var.param0, + BIOS_GET_FIELD(u8, var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER); var_data.single_sensed_fuse.vfield_ver_info.b_use_default_on_ver_check_fail = - BIOS_GET_FIELD(var.param0, + (BIOS_GET_FIELD(bool, var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL) && - (VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES != 0U); + (VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES != 0U)); var_data.single_sensed_fuse.b_fuse_value_signed = - (u8)BIOS_GET_FIELD(var.param0, + BIOS_GET_FIELD(bool, var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER); var_data.single_sensed_fuse.vfield_info.fuse_val_default = var.param1; @@ -1019,26 +1022,38 @@ static int devinit_get_vfe_var_table(struct gk20a *g, case VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT: var_type = CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT; var_data.derived_product.var_idx0 = - (u8)BIOS_GET_FIELD(var.param0, + BIOS_GET_FIELD(u8, var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0); var_data.derived_product.var_idx1 = - (u8)BIOS_GET_FIELD(var.param0, + BIOS_GET_FIELD(u8, var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1); break; case VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM: var_type = CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM; var_data.derived_sum.var_idx0 = - (u8)BIOS_GET_FIELD(var.param0, + BIOS_GET_FIELD(u8, var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0); var_data.derived_sum.var_idx1 = - (u8)BIOS_GET_FIELD(var.param0, + BIOS_GET_FIELD(u8, var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1); break; default: status = -EINVAL; + done = true; + break; + } + /* + * Previously we were doing "goto done" from the default case of + * the switch-case block above. MISRA however, gets upset about + * this because it wants a break statement in the default case. + * That's why we had to move the goto statement outside of the + * switch-case block. + */ + if(done) { goto done; } + var_data.board_obj.type = var_type; var_data.board_obj.type_mask = 0; diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index a3caa1a14..29311be3e 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c @@ -379,13 +379,13 @@ static int parse_pstate_entry_5x(struct gk20a *g, pclksetinfo->clkwhich = clk_domain->domain; pclksetinfo->nominal_mhz = - BIOS_GET_FIELD(clk_entry->param0, + BIOS_GET_FIELD(u32, clk_entry->param0, VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ); pclksetinfo->min_mhz = - BIOS_GET_FIELD(clk_entry->param1, + BIOS_GET_FIELD(u16, clk_entry->param1, VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ); pclksetinfo->max_mhz = - BIOS_GET_FIELD(clk_entry->param1, + BIOS_GET_FIELD(u16, clk_entry->param1, VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ); nvgpu_log_info(g, diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c index 33730ff7e..6e0522fd4 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/volt/volt_dev.c @@ -225,14 +225,14 @@ static int volt_get_voltage_device_table_1x_psv(struct gk20a *g, return -ENOMEM; } - frequency_hz = (u32)BIOS_GET_FIELD(p_bios_entry->param0, - NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY); + frequency_hz = BIOS_GET_FIELD(u32, p_bios_entry->param0, + NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY); - ext_dev_idx = (u8)BIOS_GET_FIELD(p_bios_entry->param0, - NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX); + ext_dev_idx = BIOS_GET_FIELD(u8, p_bios_entry->param0, + NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX); ptmp_dev->super.operation_type = volt_dev_operation_type_convert( - (u8)BIOS_GET_FIELD(p_bios_entry->param1, + BIOS_GET_FIELD(u8, p_bios_entry->param1, NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE)); if (ptmp_dev->super.operation_type == @@ -243,25 +243,25 @@ static int volt_get_voltage_device_table_1x_psv(struct gk20a *g, goto done; } - ptmp_dev->super.voltage_min_uv = - (u32)BIOS_GET_FIELD(p_bios_entry->param1, - NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM); + ptmp_dev->super.voltage_min_uv = BIOS_GET_FIELD(u32, + p_bios_entry->param1, + NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM); - ptmp_dev->super.voltage_max_uv = - (u32)BIOS_GET_FIELD(p_bios_entry->param2, - NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM); + ptmp_dev->super.voltage_max_uv = BIOS_GET_FIELD(u32, + p_bios_entry->param2, + NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM); - ptmp_dev->voltage_base_uv = BIOS_GET_FIELD(p_bios_entry->param3, - NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE); + ptmp_dev->voltage_base_uv = BIOS_GET_FIELD(s32, p_bios_entry->param3, + NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE); - steps = (u8)BIOS_GET_FIELD(p_bios_entry->param3, - NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS); + steps = BIOS_GET_FIELD(u8, p_bios_entry->param3, + NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS); if (steps == VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID) { steps = VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT; } ptmp_dev->voltage_offset_scale_uv = - BIOS_GET_FIELD(p_bios_entry->param4, + BIOS_GET_FIELD(s32, p_bios_entry->param4, NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE); volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g, diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c index d5a317b5b..47a0e794f 100644 --- a/drivers/gpu/nvgpu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/volt/volt_policy.c @@ -349,35 +349,35 @@ static int volt_get_volt_policy_table(struct gk20a *g, switch (policy_type) { case CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP: policy_type_data.split_rail.rail_idx_master = - (u8)BIOS_GET_FIELD(entry.param0, - NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER); + BIOS_GET_FIELD(u8, entry.param0, + NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER); policy_type_data.split_rail.rail_idx_slave = - (u8)BIOS_GET_FIELD(entry.param0, - NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE); + BIOS_GET_FIELD(u8, entry.param0, + NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE); policy_type_data.split_rail.delta_min_vfe_equ_idx = - (u8)BIOS_GET_FIELD(entry.param0, - NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN); + BIOS_GET_FIELD(u8, entry.param0, + NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN); policy_type_data.split_rail.delta_max_vfe_equ_idx = - (u8)BIOS_GET_FIELD(entry.param0, - NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX); + BIOS_GET_FIELD(u8, entry.param0, + NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX); break; case CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP: policy_type_data.single_rail_ms.inter_switch_delay_us = - (u16)BIOS_GET_FIELD(entry.param1, - NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE); + BIOS_GET_FIELD(u16, entry.param1, + NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE); policy_type_data.single_rail_ms.ramp_up_step_size_uv = - (u32)BIOS_GET_FIELD(entry.param2, - NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV); + BIOS_GET_FIELD(u32, entry.param2, + NV_VBIOS_VPT_ENTRY_PARAM2_SR_RAMP_UP_STEP_SIZE_UV); policy_type_data.single_rail_ms.ramp_down_step_size_uv = - (u32)BIOS_GET_FIELD(entry.param3, - NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV); + BIOS_GET_FIELD(u32, entry.param3, + NV_VBIOS_VPT_ENTRY_PARAM3_SR_RAMP_DOWN_STEP_SIZE_UV); break; case CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL: policy_type_data.single_rail.rail_idx = - (u8)BIOS_GET_FIELD(entry.param0, + BIOS_GET_FIELD(u8, entry.param0, NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN); break; }