diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml
index 4d2980750..b5771d2ee 100644
--- a/arch/nvgpu-common.yaml
+++ b/arch/nvgpu-common.yaml
@@ -781,12 +781,6 @@ pmu:
           sources: [ common/pmu/clk/clk_fll.c,
                      include/nvgpu/pmu/clk/clk_fll.h ]
 
-        freq_controller:
-          safe: yes
-          gpu: dgpu
-          sources: [ common/pmu/clk/clk_freq_controller.c,
-                     common/pmu/clk/clk_freq_controller.h,
-                     include/nvgpu/pmu/clk/clk_freq_controller.h ]
         prog:
           safe: yes
           gpu: dgpu
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 251711504..256184446 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -177,7 +177,6 @@ nvgpu-y += \
 	common/pmu/clk/clk_freq_domain.o \
 	common/pmu/clk/clk_prog.o \
 	common/pmu/clk/clk_vf_point.o \
-	common/pmu/clk/clk_freq_controller.o \
 	common/pmu/clk/clk.o \
 	common/pmu/boardobj/boardobj.o \
 	common/pmu/boardobj/boardobjgrp.o \
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index af2f4b6d6..ad1622ed9 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -437,7 +437,6 @@ srcs += \
 	common/pmu/clk/clk_domain.c \
 	common/pmu/clk/clk_freq_domain.c \
 	common/pmu/clk/clk_fll.c \
-	common/pmu/clk/clk_freq_controller.c \
 	common/pmu/clk/clk_prog.c \
 	common/pmu/clk/clk_vf_point.c \
 	common/pmu/clk/clk_vin.c \
diff --git a/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gp10b.c b/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gp10b.c
index d7a647e0d..cf669e3e2 100644
--- a/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gp10b.c
+++ b/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gp10b.c
@@ -27,8 +27,7 @@
 
 bool gp10b_check_clk_arb_support(struct gk20a *g)
 {
-	if (g->ops.clk_arb.get_arbiter_clk_domains != NULL ||
-		g->ops.clk.support_clk_freq_controller){
+	if (g->ops.clk_arb.get_arbiter_clk_domains != NULL) {
 		return true;
 	}
 	else {
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c
deleted file mode 100644
index 646afa711..000000000
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.c
+++ /dev/null
@@ -1,571 +0,0 @@
-/*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <nvgpu/bios.h>
-#include <nvgpu/bug.h>
-#include <nvgpu/gk20a.h>
-#include <nvgpu/boardobjgrp.h>
-#include <nvgpu/boardobjgrp_e32.h>
-#include <nvgpu/pmu/boardobjgrp_classes.h>
-#include <nvgpu/boardobjgrpmask.h>
-#include <nvgpu/boardobj.h>
-#include <nvgpu/string.h>
-#include <nvgpu/pmu/pmuif/ctrlclk.h>
-#include <nvgpu/pmu/pmuif/ctrlvolt.h>
-#include <nvgpu/pmu/clk/clk.h>
-#include <nvgpu/pmu/clk/clk_fll.h>
-#include <nvgpu/pmu/clk/clk_domain.h>
-#include <nvgpu/pmu/clk/clk_freq_controller.h>
-#include <nvgpu/pmu/cmd.h>
-
-#include "clk_freq_controller.h"
-
-static int clk_freq_controller_pmudatainit_super(struct gk20a *g,
-	struct boardobj *board_obj_ptr,
-	struct nv_pmu_boardobj *ppmudata)
-{
-	struct nv_pmu_clk_clk_freq_controller_boardobj_set *pfreq_cntlr_set;
-	struct clk_freq_controller *pfreq_cntlr;
-	int status = 0;
-
-	status = nvgpu_boardobj_pmu_data_init_super(g, board_obj_ptr, ppmudata);
-	if (status != 0) {
-		return status;
-	}
-
-	pfreq_cntlr_set =
-		(struct nv_pmu_clk_clk_freq_controller_boardobj_set *)ppmudata;
-	pfreq_cntlr    = (struct clk_freq_controller *)board_obj_ptr;
-
-	pfreq_cntlr_set->controller_id = pfreq_cntlr->controller_id;
-	pfreq_cntlr_set->clk_domain = pfreq_cntlr->clk_domain;
-	pfreq_cntlr_set->parts_freq_mode = pfreq_cntlr->parts_freq_mode;
-	pfreq_cntlr_set->bdisable = pfreq_cntlr->bdisable;
-	pfreq_cntlr_set->freq_cap_noise_unaware_vmin_above =
-		pfreq_cntlr->freq_cap_noise_unaware_vmin_above;
-	pfreq_cntlr_set->freq_cap_noise_unaware_vmin_below =
-		pfreq_cntlr->freq_cap_noise_unaware_vmin_below;
-	pfreq_cntlr_set->freq_hyst_pos_mhz = pfreq_cntlr->freq_hyst_pos_mhz;
-	pfreq_cntlr_set->freq_hyst_neg_mhz = pfreq_cntlr->freq_hyst_neg_mhz;
-
-	return status;
-}
-
-static int clk_freq_controller_pmudatainit_pi(struct gk20a *g,
-	struct boardobj *board_obj_ptr,
-	struct nv_pmu_boardobj *ppmudata)
-{
-	struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set
-		*pfreq_cntlr_pi_set;
-	struct clk_freq_controller_pi *pfreq_cntlr_pi;
-	int status = 0;
-
-	status = clk_freq_controller_pmudatainit_super(g,
-		board_obj_ptr, ppmudata);
-	if (status != 0) {
-		return -1;
-	}
-
-	pfreq_cntlr_pi_set =
-		(struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set *)
-		ppmudata;
-	pfreq_cntlr_pi = (struct clk_freq_controller_pi *)board_obj_ptr;
-
-	pfreq_cntlr_pi_set->prop_gain = pfreq_cntlr_pi->prop_gain;
-	pfreq_cntlr_pi_set->integ_gain = pfreq_cntlr_pi->integ_gain;
-	pfreq_cntlr_pi_set->integ_decay = pfreq_cntlr_pi->integ_decay;
-	pfreq_cntlr_pi_set->volt_delta_min = pfreq_cntlr_pi->volt_delta_min;
-	pfreq_cntlr_pi_set->volt_delta_max = pfreq_cntlr_pi->volt_delta_max;
-	pfreq_cntlr_pi_set->slowdown_pct_min = pfreq_cntlr_pi->slowdown_pct_min;
-	pfreq_cntlr_pi_set->bpoison = pfreq_cntlr_pi->bpoison;
-
-	return status;
-}
-
-static int clk_freq_controller_construct_super(struct gk20a *g,
-	struct boardobj **ppboardobj,
-	size_t size, void *pargs)
-{
-	struct clk_freq_controller *pfreq_cntlr = NULL;
-	struct clk_freq_controller *pfreq_cntlr_tmp = NULL;
-	int status = 0;
-
-	status = nvgpu_boardobj_construct_super(g, ppboardobj, size, pargs);
-	if (status != 0) {
-		return -EINVAL;
-	}
-
-	pfreq_cntlr_tmp = (struct clk_freq_controller *)pargs;
-	pfreq_cntlr = (struct clk_freq_controller *)*ppboardobj;
-
-	pfreq_cntlr->super.pmudatainit = clk_freq_controller_pmudatainit_super;
-
-	pfreq_cntlr->controller_id   = pfreq_cntlr_tmp->controller_id;
-	pfreq_cntlr->clk_domain      = pfreq_cntlr_tmp->clk_domain;
-	pfreq_cntlr->parts_freq_mode  = pfreq_cntlr_tmp->parts_freq_mode;
-	pfreq_cntlr->freq_cap_noise_unaware_vmin_above  =
-		pfreq_cntlr_tmp->freq_cap_noise_unaware_vmin_above;
-	pfreq_cntlr->freq_cap_noise_unaware_vmin_below  =
-		pfreq_cntlr_tmp->freq_cap_noise_unaware_vmin_below;
-	pfreq_cntlr->freq_hyst_pos_mhz = pfreq_cntlr_tmp->freq_hyst_pos_mhz;
-	pfreq_cntlr->freq_hyst_neg_mhz = pfreq_cntlr_tmp->freq_hyst_neg_mhz;
-
-	return status;
-}
-
-static int clk_freq_controller_construct_pi(struct gk20a *g,
-	struct boardobj **ppboardobj,
-	size_t size, void *pargs)
-{
-	struct clk_freq_controller_pi *pfreq_cntlr_pi = NULL;
-	struct clk_freq_controller_pi *pfreq_cntlr_pi_tmp = NULL;
-	int status = 0;
-
-	status = clk_freq_controller_construct_super(g, ppboardobj,
-			size, pargs);
-	if (status != 0) {
-		return -EINVAL;
-	}
-
-	pfreq_cntlr_pi = (struct clk_freq_controller_pi *)*ppboardobj;
-	pfreq_cntlr_pi_tmp = (struct clk_freq_controller_pi *)pargs;
-
-	pfreq_cntlr_pi->super.super.pmudatainit =
-		clk_freq_controller_pmudatainit_pi;
-
-	pfreq_cntlr_pi->prop_gain = pfreq_cntlr_pi_tmp->prop_gain;
-	pfreq_cntlr_pi->integ_gain = pfreq_cntlr_pi_tmp->integ_gain;
-	pfreq_cntlr_pi->integ_decay = pfreq_cntlr_pi_tmp->integ_decay;
-	pfreq_cntlr_pi->volt_delta_min = pfreq_cntlr_pi_tmp->volt_delta_min;
-	pfreq_cntlr_pi->volt_delta_max = pfreq_cntlr_pi_tmp->volt_delta_max;
-	pfreq_cntlr_pi->slowdown_pct_min = pfreq_cntlr_pi_tmp->slowdown_pct_min;
-	pfreq_cntlr_pi->bpoison = pfreq_cntlr_pi_tmp->bpoison;
-
-	return status;
-}
-
-static struct clk_freq_controller *clk_clk_freq_controller_construct(
-	struct gk20a *g,
-	void *pargs)
-{
-	struct boardobj *board_obj_ptr = NULL;
-	int status = 0;
-
-	if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI) {
-		return NULL;
-	}
-
-	status = clk_freq_controller_construct_pi(g, &board_obj_ptr,
-			sizeof(struct clk_freq_controller_pi), pargs);
-	if (status != 0) {
-		return NULL;
-	}
-
-	return (struct clk_freq_controller *)board_obj_ptr;
-}
-
-
-static int clk_get_freq_controller_table(struct gk20a *g,
-		struct nvgpu_clk_freq_controllers *pclk_freq_controllers)
-{
-	int status = 0;
-	u8 *pfreq_controller_table_ptr = NULL;
-	struct vbios_fct_1x_header header = { 0 };
-	struct vbios_fct_1x_entry entry  = { 0 };
-	u8 entry_idx;
-	u8 *entry_offset;
-	struct clk_freq_controller *pclk_freq_cntr = NULL;
-	struct clk_freq_controller *ptmp_freq_cntr = NULL;
-	struct clk_freq_controller_pi *ptmp_freq_cntr_pi = NULL;
-	struct nvgpu_clk_domain *pclk_domain;
-
-	struct freq_controller_data_type {
-		union {
-			struct boardobj board_obj;
-			struct clk_freq_controller freq_controller;
-			struct clk_freq_controller_pi  freq_controller_pi;
-		};
-	} freq_controller_data;
-
-	pfreq_controller_table_ptr =
-		(u8 *)nvgpu_bios_get_perf_table_ptrs(g,
-			nvgpu_bios_get_bit_token(g, NVGPU_BIOS_CLOCK_TOKEN),
-			FREQUENCY_CONTROLLER_TABLE);
-	if (pfreq_controller_table_ptr == NULL) {
-		status = -EINVAL;
-		goto done;
-	}
-
-	nvgpu_memcpy((u8 *)&header, pfreq_controller_table_ptr,
-			sizeof(struct vbios_fct_1x_header));
-
-	pclk_freq_controllers->sampling_period_ms = header.sampling_period_ms;
-	pclk_freq_controllers->volt_policy_idx = 0;
-
-	/* Read in the entries. */
-	for (entry_idx = 0; entry_idx < header.entry_count; entry_idx++) {
-		entry_offset = (pfreq_controller_table_ptr +
-			header.header_size + (entry_idx * header.entry_size));
-
-		(void) memset(&freq_controller_data, 0x0,
-				sizeof(struct freq_controller_data_type));
-		ptmp_freq_cntr = &freq_controller_data.freq_controller;
-		ptmp_freq_cntr_pi = &freq_controller_data.freq_controller_pi;
-
-		nvgpu_memcpy((u8 *)&entry, entry_offset,
-			sizeof(struct vbios_fct_1x_entry));
-
-		if (!BIOS_GET_FIELD(bool, entry.flags0,
-				NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE)) {
-			continue;
-		}
-
-		freq_controller_data.board_obj.type = BIOS_GET_FIELD(u8,
-			entry.flags0, NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE);
-
-		ptmp_freq_cntr->controller_id =
-			BIOS_GET_FIELD(u8, entry.param0,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID);
-
-		pclk_domain = g->pmu->clk_pmu->clk_get_clk_domain(
-				(g->pmu->clk_pmu),
-				(u32)entry.clk_domain_idx);
-		freq_controller_data.freq_controller.clk_domain =
-			pclk_domain->api_domain;
-
-		ptmp_freq_cntr->parts_freq_mode =
-			BIOS_GET_FIELD(u8, entry.param0,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE);
-
-		/* Populate PI specific data */
-		ptmp_freq_cntr_pi->slowdown_pct_min =
-			BIOS_GET_FIELD(u8, entry.param1,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN);
-
-		ptmp_freq_cntr_pi->bpoison =
-			BIOS_GET_FIELD(bool, entry.param1,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON);
-
-		ptmp_freq_cntr_pi->prop_gain =
-			BIOS_GET_FIELD(s32, entry.param2,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN);
-
-		ptmp_freq_cntr_pi->integ_gain =
-			BIOS_GET_FIELD(s32, entry.param3,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN);
-
-		ptmp_freq_cntr_pi->integ_decay =
-			BIOS_GET_FIELD(s32, entry.param4,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY);
-
-		ptmp_freq_cntr_pi->volt_delta_min =
-			BIOS_GET_FIELD(s32, entry.param5,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN);
-
-		ptmp_freq_cntr_pi->volt_delta_max =
-			BIOS_GET_FIELD(s32, entry.param6,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX);
-
-		ptmp_freq_cntr->freq_cap_noise_unaware_vmin_above =
-			BIOS_GET_FIELD(s16, entry.param7,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF);
-
-		ptmp_freq_cntr->freq_cap_noise_unaware_vmin_below =
-			BIOS_GET_FIELD(s16, entry.param7,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN);
-
-		ptmp_freq_cntr->freq_hyst_pos_mhz =
-			BIOS_GET_FIELD(s16, entry.param8,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS);
-		ptmp_freq_cntr->freq_hyst_neg_mhz =
-			BIOS_GET_FIELD(s16, entry.param8,
-				NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG);
-
-		if (ptmp_freq_cntr_pi->volt_delta_max <
-			ptmp_freq_cntr_pi->volt_delta_min) {
-			goto done;
-		}
-
-		pclk_freq_cntr = clk_clk_freq_controller_construct(g,
-						(void *)&freq_controller_data);
-
-		if (pclk_freq_cntr == NULL) {
-			nvgpu_err(g,
-				"unable to construct clock freq cntlr boardobj for %d",
-				entry_idx);
-			status = -EINVAL;
-			goto done;
-		}
-
-		status = boardobjgrp_objinsert(
-				&pclk_freq_controllers->super.super,
-				(struct boardobj *)pclk_freq_cntr, entry_idx);
-		if (status != 0) {
-			nvgpu_err(g,
-			"unable to insert clock freq cntlr boardobj for");
-			status = -EINVAL;
-			goto done;
-		}
-
-	}
-
-done:
-	return status;
-}
-
-int nvgpu_clk_freq_controller_pmu_setup(struct gk20a *g)
-{
-	int status;
-	struct boardobjgrp *pboardobjgrp = NULL;
-
-	nvgpu_log_info(g, " ");
-
-	pboardobjgrp = &g->pmu->clk_pmu->clk_freq_controllers->super.super;
-
-	if (!pboardobjgrp->bconstructed) {
-		return -EINVAL;
-	}
-
-	status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
-
-	nvgpu_log_info(g, "Done");
-	return status;
-}
-
-static int _clk_freq_controller_devgrp_pmudata_instget(struct gk20a *g,
-		struct nv_pmu_boardobjgrp *pmuboardobjgrp,
-		struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx)
-{
-	struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set *pgrp_set =
-		(struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set *)
-		pmuboardobjgrp;
-
-	nvgpu_log_info(g, " ");
-
-	/*check whether pmuboardobjgrp has a valid boardobj in index*/
-	if (((u32)BIT(idx) &
-		pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) {
-		return -EINVAL;
-	}
-
-	*ppboardobjpmudata = (struct nv_pmu_boardobj *)
-		&pgrp_set->objects[idx].data.board_obj;
-	nvgpu_log_info(g, " Done");
-	return 0;
-}
-
-static int _clk_freq_controllers_pmudatainit(struct gk20a *g,
-		struct boardobjgrp *pboardobjgrp,
-		struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
-{
-	struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header *pset =
-		(struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header *)
-		pboardobjgrppmu;
-	struct nvgpu_clk_freq_controllers *pcntrs =
-		(struct nvgpu_clk_freq_controllers *)pboardobjgrp;
-	int status = 0;
-
-	status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
-	if (status != 0) {
-		nvgpu_err(g,
-			"error updating pmu boardobjgrp for clk freq ctrs 0x%x",
-			 status);
-		goto done;
-	}
-	pset->sampling_period_ms = pcntrs->sampling_period_ms;
-	pset->volt_policy_idx = pcntrs->volt_policy_idx;
-
-done:
-	return status;
-}
-
-int nvgpu_clk_freq_controller_sw_setup(struct gk20a *g)
-{
-	int status = 0;
-	struct boardobjgrp *pboardobjgrp = NULL;
-	struct nvgpu_clk_freq_controllers *pclk_freq_controllers;
-	struct nvgpu_avfsfllobjs *pfllobjs = g->pmu->clk_pmu->avfs_fllobjs;
-	struct fll_device *pfll;
-	struct clk_freq_controller *pclkfreqctrl;
-	u8 i;
-	u8 j;
-
-	nvgpu_log_info(g, " ");
-
-
-	pclk_freq_controllers = g->pmu->clk_pmu->clk_freq_controllers;
-	status = nvgpu_boardobjgrp_construct_e32(g,
-			&pclk_freq_controllers->super);
-	if (status != 0) {
-		nvgpu_err(g,
-			"error creating boardobjgrp for clk FCT, status - 0x%x",
-			status);
-		goto done;
-	}
-
-	pboardobjgrp = &g->pmu->clk_pmu->clk_freq_controllers->super.super;
-
-	pboardobjgrp->pmudatainit  = _clk_freq_controllers_pmudatainit;
-	pboardobjgrp->pmudatainstget  =
-			_clk_freq_controller_devgrp_pmudata_instget;
-	pboardobjgrp->pmustatusinstget  = NULL;
-
-	/* Initialize mask to zero.*/
-	status = boardobjgrpmask_e32_init(
-			&pclk_freq_controllers->freq_ctrl_load_mask, NULL);
-	if (status != 0) {
-		nvgpu_err(g, "boardobjgrpmask_e32_init failed err=%d", status);
-		goto done;
-	}
-
-	BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_FREQ_CONTROLLER);
-
-	status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
-			clk, CLK, clk_freq_controller, CLK_FREQ_CONTROLLER);
-	if (status != 0) {
-		nvgpu_err(g,
-			"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
-			status);
-		goto done;
-	}
-
-	status = clk_get_freq_controller_table(g, pclk_freq_controllers);
-	if (status != 0) {
-		nvgpu_err(g, "error reading freq controller table - 0x%x",
-			status);
-		goto done;
-	}
-
-	BOARDOBJGRP_FOR_EACH(&(pclk_freq_controllers->super.super),
-			     struct clk_freq_controller *, pclkfreqctrl, i) {
-		pfll = NULL;
-		j = 0;
-		BOARDOBJGRP_FOR_EACH(&(pfllobjs->super.super),
-			     struct fll_device *, pfll, j) {
-			if (pclkfreqctrl->controller_id == pfll->id) {
-				pfll->freq_ctrl_idx = i;
-				break;
-			}
-		}
-		status = nvgpu_boardobjgrpmask_bit_set(&pclk_freq_controllers->
-			freq_ctrl_load_mask.super, i);
-		if (status != 0) {
-			nvgpu_err(g, "boardobjgrpmask_bitset failed err=%d",
-				status);
-			goto done;
-		}
-	}
-done:
-		nvgpu_log_info(g, " done status %x", status);
-		return status;
-}
-
-int nvgpu_clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
-{
-	int status;
-	struct nvgpu_pmu *pmu = g->pmu;
-	struct nv_pmu_rpc_struct_clk_load clk_load_rpc;
-	struct nvgpu_clk_freq_controllers *pclk_freq_controllers;
-	struct ctrl_boardobjgrp_mask_e32 *load_mask;
-	struct boardobjgrpmask_e32 isolate_cfc_mask;
-
-	(void) memset(&clk_load_rpc, 0,
-			sizeof(struct nv_pmu_rpc_struct_clk_load));
-
-	pclk_freq_controllers = g->pmu->clk_pmu->clk_freq_controllers;
-	load_mask = &clk_load_rpc.clk_load.payload.freq_controllers.load_mask;
-	status = boardobjgrpmask_e32_init(&isolate_cfc_mask, NULL);
-	if (status != 0) {
-		nvgpu_err(g, "Error initializing group mask");
-		goto done;
-	}
-
-	clk_load_rpc.clk_load.feature =
-			NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER;
-	clk_load_rpc.clk_load.action_mask = bload ?
-		NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES :
-		NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO;
-
-	if (bit_idx == CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL) {
-		status = nvgpu_boardobjgrpmask_export(
-				&pclk_freq_controllers->
-					freq_ctrl_load_mask.super,
-				pclk_freq_controllers->
-					freq_ctrl_load_mask.super.bitcount,
-				&load_mask->super);
-	} else {
-		status = nvgpu_boardobjgrpmask_bit_set(&isolate_cfc_mask.super,
-						bit_idx);
-		status = nvgpu_boardobjgrpmask_export(&isolate_cfc_mask.super,
-					isolate_cfc_mask.super.bitcount,
-					&load_mask->super);
-		if (bload) {
-			status = nvgpu_boardobjgrpmask_bit_set(
-					&pclk_freq_controllers->
-						freq_ctrl_load_mask.super,
-					bit_idx);
-		} else {
-			status = nvgpu_boardobjgrpmask_bit_clr(
-					&pclk_freq_controllers->
-						freq_ctrl_load_mask.super,
-					bit_idx);
-		}
-	}
-
-	if (status != 0) {
-		nvgpu_err(g, "Error in generating mask used to select CFC");
-		goto done;
-	}
-
-	/* Continue with PMU setup, assume FB map is done  */
-	PMU_RPC_EXECUTE_CPB(status, pmu, CLK, LOAD, &clk_load_rpc, 0);
-	if (status != 0) {
-		nvgpu_err(g,
-			"Failed to execute Clk freq ctrl Load RPC status=0x%x",
-			status);
-	}
-
-done:
-	return status;
-}
-
-int nvgpu_clk_freq_controller_init_pmupstate(struct gk20a *g)
-{
-	/* If already allocated, do not re-allocate */
-	if (g->pmu->clk_pmu->clk_freq_controllers != NULL) {
-		return 0;
-	}
-
-	g->pmu->clk_pmu->clk_freq_controllers = nvgpu_kzalloc(g,
-			sizeof(*g->pmu->clk_pmu->clk_freq_controllers));
-	if (g->pmu->clk_pmu->clk_freq_controllers == NULL) {
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-void nvgpu_clk_freq_controller_free_pmupstate(struct gk20a *g)
-{
-	nvgpu_kfree(g, g->pmu->clk_pmu->clk_freq_controllers);
-	g->pmu->clk_pmu->clk_freq_controllers = NULL;
-}
diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.h b/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.h
deleted file mode 100644
index 86fad6a92..000000000
--- a/drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
-* Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
-*
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef NVGPU_CLK_FREQ_CONTROLLER_H
-#define NVGPU_CLK_FREQ_CONTROLLER_H
-
-#include <nvgpu/boardobj.h>
-
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL  0xFFU
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS  0x00U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC  0x01U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR 0x02U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0 0x03U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1 0x04U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2 0x05U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3 0x06U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4 0x07U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5 0x08U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPCS 0x09U
-
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_MASK_UNICAST_GPC     \
-			(BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0) | \
-			BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1) | \
-			BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2) | \
-			BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3) | \
-			BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4) | \
-			BIT32(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5))
-
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_DISABLED  0x00U
-#define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI        0x01U
-
-
-struct clk_freq_controller {
-	struct boardobj    super;
-	u8   controller_id;
-	u8   parts_freq_mode;
-	bool bdisable;
-	u32  clk_domain;
-	s16  freq_cap_noise_unaware_vmin_above;
-	s16  freq_cap_noise_unaware_vmin_below;
-	s16  freq_hyst_pos_mhz;
-	s16  freq_hyst_neg_mhz;
-};
-
-struct clk_freq_controller_pi {
-	struct clk_freq_controller super;
-	s32 prop_gain;
-	s32 integ_gain;
-	s32 integ_decay;
-	s32 volt_delta_min;
-	s32 volt_delta_max;
-	u8  slowdown_pct_min;
-	bool bpoison;
-};
-
-#endif /* NVGPU_CLK_FREQ_CONTROLLER_H */
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c
index cf7430379..e11615fb1 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c
@@ -34,7 +34,6 @@
 #include <nvgpu/pmu/clk/clk_vin.h>
 #include <nvgpu/pmu/clk/clk_domain.h>
 #include <nvgpu/pmu/clk/clk_prog.h>
-#include <nvgpu/pmu/clk/clk_freq_controller.h>
 #include <nvgpu/pmu/clk/clk_freq_domain.h>
 #include <nvgpu/pmu/clk/clk_vf_point.h>
 #include <nvgpu/pmu/pmgr.h>
@@ -58,7 +57,6 @@ void nvgpu_pmu_pstate_deinit(struct gk20a *g)
 		nvgpu_clk_prog_free_pmupstate(g);
 		nvgpu_clk_vf_point_free_pmupstate(g);
 		nvgpu_clk_freq_domain_free_pmupstate(g);
-		nvgpu_clk_freq_controller_free_pmupstate(g);
 		nvgpu_clk_fll_free_pmupstate(g);
 		nvgpu_clk_vin_free_pmupstate(g);
 		nvgpu_clk_free_pmupstate(g);
@@ -104,12 +102,6 @@ static int pmu_pstate_clk_init(struct gk20a *g)
 		return err;
 	}
 
-	err = nvgpu_clk_freq_controller_init_pmupstate(g);
-	if (err != 0) {
-		nvgpu_clk_freq_controller_free_pmupstate(g);
-		return err;
-	}
-
 	err = nvgpu_clk_vin_init_pmupstate(g);
 	if (err != 0) {
 		nvgpu_clk_vin_free_pmupstate(g);
@@ -225,14 +217,6 @@ static int pmu_pstate_clk_sw_setup(struct gk20a *g)
 		}
 	}
 
-	if (g->ops.clk.support_clk_freq_controller) {
-		err = nvgpu_clk_freq_controller_sw_setup(g);
-		if (err != 0) {
-			nvgpu_clk_freq_controller_free_pmupstate(g);
-			return err;
-		}
-	}
-
 	return 0;
 }
 
@@ -398,13 +382,6 @@ static int pmu_pstate_clk_pmu_setup(struct gk20a *g)
 		return err;
 	}
 
-	if (g->ops.clk.support_clk_freq_controller) {
-		err = nvgpu_clk_freq_controller_pmu_setup(g);
-		if (err != 0) {
-			return err;
-		}
-	}
-
 	if (g->ops.clk.support_vf_point &&
 		g->ops.pmu_perf.support_vfe) {
 		err = nvgpu_clk_vf_point_pmu_setup(g);
diff --git a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h
index 17dd342b4..fe943c021 100644
--- a/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h
+++ b/drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h
@@ -127,8 +127,6 @@ struct nv_pmu_super_surface {
 				clk_vin_device_grp_set;
 			struct nv_pmu_clk_clk_domain_boardobj_grp_set
 				clk_domain_grp_set;
-			struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set
-				clk_freq_controller_grp_set;
 			struct nv_pmu_clk_clk_fll_device_boardobj_grp_set
 				clk_fll_device_grp_set;
 			struct nv_pmu_clk_clk_prog_boardobj_grp_set
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index d4f8e3bd7..0cfc2ef1c 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -1648,7 +1648,6 @@ int tu104_init_hal(struct gk20a *g)
 	nvgpu_set_enabled(g, NVGPU_SUPPORT_DGPU_PCIE_SCRIPT_EXECUTE, true);
 
 	/* for now */
-	gops->clk.support_clk_freq_controller = false;
 	gops->clk.support_pmgr_domain = false;
 	gops->clk.support_lpwr_pg = false;
 	gops->clk.support_clk_freq_domain = false;
@@ -1686,8 +1685,6 @@ int tu104_init_hal(struct gk20a *g)
 #ifdef CONFIG_NVGPU_CLK_ARB
 		gops->clk_arb.get_arbiter_clk_domains = NULL;
 #endif
-		gops->clk.support_clk_freq_controller = false;
-
 	} else
 #endif
 	{
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
index ea5386b71..aedf045d2 100644
--- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
@@ -930,10 +930,7 @@ int vgpu_gp10b_init_hal(struct gk20a *g)
 	gops->get_litter_value = vgpu_gp10b_ops.get_litter_value;
 	gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
 
-	if (priv->constants.can_set_clkrate) {
-		gops->clk.support_clk_freq_controller = true;
-	} else {
-		gops->clk.support_clk_freq_controller = false;
+	if (!priv->constants.can_set_clkrate) {
 		gops->clk_arb.get_arbiter_clk_domains = NULL;
 	}
 
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
index 855504c18..b6bcef594 100644
--- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
@@ -1047,10 +1047,7 @@ int vgpu_gv11b_init_hal(struct gk20a *g)
 	gops->get_litter_value = vgpu_gv11b_ops.get_litter_value;
 	gops->semaphore_wakeup = nvgpu_channel_semaphore_wakeup;
 
-	if (priv->constants.can_set_clkrate) {
-		gops->clk.support_clk_freq_controller = true;
-	} else {
-		gops->clk.support_clk_freq_controller = false;
+	if (!priv->constants.can_set_clkrate) {
 		gops->clk_arb.get_arbiter_clk_domains = NULL;
 	}
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 778d37355..12f887489 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -431,7 +431,6 @@ struct gpu_ops {
 		void (*get_change_seq_time)(struct gk20a *g, s64 *change_time);
 		void (*change_host_clk_source)(struct gk20a *g);
 		bool split_rail_support;
-		bool support_clk_freq_controller;
 		bool support_pmgr_domain;
 		bool support_lpwr_pg;
 		int (*perf_pmu_vfe_load)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
index ab22d276d..96bd99034 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
@@ -33,7 +33,6 @@ struct nvgpu_clk_domains;
 struct nvgpu_clk_progs;
 struct nvgpu_clk_vf_points;
 struct nvgpu_clk_mclk_state;
-struct nvgpu_clk_freq_controllers;
 struct nvgpu_clk_freq_domain_grp;
 struct nvgpu_clk_slave_freq;
 struct ctrl_perf_change_seq_change_input;
@@ -75,7 +74,6 @@ struct nvgpu_clk_pmupstate {
 	struct nvgpu_clk_domains *clk_domainobjs;
 	struct nvgpu_clk_progs *clk_progobjs;
 	struct nvgpu_clk_vf_points *clk_vf_pointobjs;
-	struct nvgpu_clk_freq_controllers *clk_freq_controllers;
 	struct nvgpu_clk_freq_domain_grp *freq_domain_grp_objs;
 
 	/* clk_domain unit functions */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h
deleted file mode 100644
index 85b468a8d..000000000
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * general clock structures & definitions
- *
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef NVGPU_PMU_CLK_FREQ_CONTROLLER_H
-#define NVGPU_PMU_CLK_FREQ_CONTROLLER_H
-
-#include <nvgpu/types.h>
-#include <nvgpu/boardobjgrpmask.h>
-
-struct gk20a;
-struct boardobjgrp_e32;
-
-struct nvgpu_clk_freq_controllers {
-	struct boardobjgrp_e32 super;
-	u32 sampling_period_ms;
-	struct boardobjgrpmask_e32 freq_ctrl_load_mask;
-	u8 volt_policy_idx;
-	void *pprereq_load;
-};
-
-int nvgpu_clk_freq_controller_init_pmupstate(struct gk20a *g);
-void nvgpu_clk_freq_controller_free_pmupstate(struct gk20a *g);
-int nvgpu_clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx);
-int nvgpu_clk_freq_controller_sw_setup(struct gk20a *g);
-int nvgpu_clk_freq_controller_pmu_setup(struct gk20a *g);
-
-#endif /* NVGPU_PMU_CLK_FREQ_CONTROLLER_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h
index 7cf53e2be..7c4601bfc 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h
@@ -494,17 +494,9 @@ struct nv_pmu_clk_vf_change_inject_v1 {
 
 #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES      (0x00000001U)
 
-struct nv_pmu_clk_load_payload_freq_controllers {
-	struct ctrl_boardobjgrp_mask_e32 load_mask;
-};
-
 struct nv_pmu_clk_load {
 	u8 feature;
 	u32 action_mask;
-	union {
-		struct nv_pmu_clk_load_payload_freq_controllers
-							freq_controllers;
-	} payload;
 };
 
 struct nv_pmu_clk_freq_effective_avg {
@@ -512,47 +504,6 @@ struct nv_pmu_clk_freq_effective_avg {
 	u32 freqkHz[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
 };
 
-/* CLK_FREQ_CONTROLLER */
-#define NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO	 (0x00000000U)
-#define NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002U)
-
-struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header {
-	struct nv_pmu_boardobjgrp_e32  super;
-	u32 sampling_period_ms;
-	u8 volt_policy_idx;
-};
-
-struct nv_pmu_clk_clk_freq_controller_boardobj_set {
-	struct nv_pmu_boardobj super;
-	u8   controller_id;
-	u8   parts_freq_mode;
-	bool bdisable;
-	u32  clk_domain;
-	s16  freq_cap_noise_unaware_vmin_above;
-	s16  freq_cap_noise_unaware_vmin_below;
-	s16  freq_hyst_pos_mhz;
-	s16  freq_hyst_neg_mhz;
-};
-
-struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set {
-	struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
-	s32 prop_gain;
-	s32 integ_gain;
-	s32 integ_decay;
-	s32 volt_delta_min;
-	s32 volt_delta_max;
-	u8  slowdown_pct_min;
-	bool bpoison;
-};
-
-union nv_pmu_clk_clk_freq_controller_boardobj_set_union {
-	struct nv_pmu_boardobj board_obj;
-	struct nv_pmu_clk_clk_freq_controller_boardobj_set super;
-	struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi;
-};
-
-NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller);
-
 #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_NO \
 								   (0x00000000U)
 #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_EFFECTIVE_AVG_CALLBACK_YES \
diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c b/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
index cc585169a..110e2de04 100644
--- a/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
+++ b/drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
@@ -23,13 +23,11 @@
 #include <nvgpu/boardobj.h>
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/boardobjgrp_e255.h>
-#include <nvgpu/pmu/clk/clk_freq_controller.h>
 #include <nvgpu/pmu/clk/clk_vf_point.h>
 #include <nvgpu/pmu/clk/clk_fll.h>
 #include <nvgpu/pmu/clk/clk.h>
 
 #include "hal/clk/clk_tu104.h"
-#include "common/pmu/clk/clk_freq_controller.h"
 
 void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
 
@@ -48,123 +46,6 @@ static int tu104_get_rate_show(void *data , u64 *val)
 }
 DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, tu104_get_rate_show, NULL, "%llu\n");
 
-static int sys_cfc_read(void *data , u64 *val)
-{
-	struct gk20a *g = (struct gk20a *)data;
-
-	bool bload = nvgpu_boardobjgrpmask_bit_get(
-			&g->pmu->clk_pmu->clk_freq_controllers->
-			freq_ctrl_load_mask.super,
-		CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
-
-	/* val = 1 implies CLFC is loaded or enabled */
-	*val = bload ? 1 : 0;
-	return 0;
-}
-static int sys_cfc_write(void *data , u64 val)
-{
-	struct gk20a *g = (struct gk20a *)data;
-	int status;
-	/* val = 1 implies load or enable the CLFC */
-	bool bload = val ? true : false;
-
-	nvgpu_clk_arb_pstate_change_lock(g, true);
-	status = nvgpu_clk_pmu_freq_controller_load(g, bload,
-					CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
-	nvgpu_clk_arb_pstate_change_lock(g, false);
-
-	return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n");
-
-static int ltc_cfc_read(void *data , u64 *val)
-{
-	struct gk20a *g = (struct gk20a *)data;
-
-	bool bload = nvgpu_boardobjgrpmask_bit_get(
-			&g->pmu->clk_pmu->clk_freq_controllers->
-			freq_ctrl_load_mask.super,
-		CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
-
-	/* val = 1 implies CLFC is loaded or enabled */
-	*val = bload ? 1 : 0;
-	return 0;
-}
-static int ltc_cfc_write(void *data , u64 val)
-{
-	struct gk20a *g = (struct gk20a *)data;
-	int status;
-	/* val = 1 implies load or enable the CLFC */
-	bool bload = val ? true : false;
-
-	nvgpu_clk_arb_pstate_change_lock(g, true);
-	status = nvgpu_clk_pmu_freq_controller_load(g, bload,
-					CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
-	nvgpu_clk_arb_pstate_change_lock(g, false);
-
-	return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n");
-
-static int xbar_cfc_read(void *data , u64 *val)
-{
-	struct gk20a *g = (struct gk20a *)data;
-
-	bool bload = nvgpu_boardobjgrpmask_bit_get(
-			&g->pmu->clk_pmu->clk_freq_controllers->
-			freq_ctrl_load_mask.super,
-		CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
-
-	/* val = 1 implies CLFC is loaded or enabled */
-	*val = bload ? 1 : 0;
-	return 0;
-}
-static int xbar_cfc_write(void *data , u64 val)
-{
-	struct gk20a *g = (struct gk20a *)data;
-	int status;
-	/* val = 1 implies load or enable the CLFC */
-	bool bload = val ? true : false;
-
-	nvgpu_clk_arb_pstate_change_lock(g, true);
-	status = nvgpu_clk_pmu_freq_controller_load(g, bload,
-			CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
-	nvgpu_clk_arb_pstate_change_lock(g, false);
-
-	return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read,
-			xbar_cfc_write, "%llu\n");
-
-static int gpc_cfc_read(void *data , u64 *val)
-{
-	struct gk20a *g = (struct gk20a *)data;
-
-	bool bload = nvgpu_boardobjgrpmask_bit_get(
-			&g->pmu->clk_pmu->clk_freq_controllers->
-			freq_ctrl_load_mask.super,
-		CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
-
-	/* val = 1 implies CLFC is loaded or enabled */
-	*val = bload ? 1 : 0;
-	return 0;
-}
-static int gpc_cfc_write(void *data , u64 val)
-{
-	struct gk20a *g = (struct gk20a *)data;
-	int status;
-	/* val = 1 implies load or enable the CLFC */
-	bool bload = val ? true : false;
-
-	nvgpu_clk_arb_pstate_change_lock(g, true);
-	status = nvgpu_clk_pmu_freq_controller_load(g, bload,
-			CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
-	nvgpu_clk_arb_pstate_change_lock(g, false);
-
-	return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(gpc_cfc_fops, gpc_cfc_read, gpc_cfc_write, "%llu\n");
-
 static int vftable_show(struct seq_file *s, void *unused)
 {
 	struct gk20a *g = s->private;
@@ -232,14 +113,6 @@ int tu104_clk_init_debugfs(struct gk20a *g)
 	if (clk_freq_ctlr_root == NULL)
 		return -ENOMEM;
 
-	d = debugfs_create_file("sys", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-				g, &sys_cfc_fops);
-	d = debugfs_create_file("ltc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-				g, &ltc_cfc_fops);
-	d = debugfs_create_file("xbar", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-				g, &xbar_cfc_fops);
-	d = debugfs_create_file("gpc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-				g, &gpc_cfc_fops);
 	d = debugfs_create_file("change_seq_time_us", S_IRUGO, clocks_root,
 				g, &change_seq_fops);
 
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c
index aa2cf75f5..68563943f 100644
--- a/drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c
+++ b/drivers/gpu/nvgpu/os/linux/platform_gp10b_tegra.c
@@ -173,8 +173,6 @@ static int gp10b_tegra_probe(struct device *dev)
 
 	nvgpu_mutex_init(&platform->clk_get_freq_lock);
 
-	platform->g->ops.clk.support_clk_freq_controller = true;
-
 	return 0;
 }
 
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
index 08b531ea3..838fa9e89 100644
--- a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
+++ b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
@@ -102,8 +102,6 @@ static int gv11b_tegra_probe(struct device *dev)
 
 	nvgpu_mutex_init(&platform->clk_get_freq_lock);
 
-	platform->g->ops.clk.support_clk_freq_controller = true;
-
 	return 0;
 }