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gpu: nvgpu: units: add mm.mm unit tests
This unit covers the generic functions of the mm.mm module. JIRA NVGPU-3649 Change-Id: I5b362b19e13ad3b5ba83c7c1e88411d9944be500 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2161457 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Nicolas Benech
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26
userspace/units/mm/mm/Makefile
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26
userspace/units/mm/mm/Makefile
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@@ -0,0 +1,26 @@
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# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
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# to deal in the Software without restriction, including without limitation
|
||||
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
# and/or sell copies of the Software, and to permit persons to whom the
|
||||
# Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
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# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
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# DEALINGS IN THE SOFTWARE.
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.SUFFIXES:
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OBJS = mm.o
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MODULE = mm
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include ../../Makefile.units
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35
userspace/units/mm/mm/Makefile.interface.tmk
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35
userspace/units/mm/mm/Makefile.interface.tmk
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@@ -0,0 +1,35 @@
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################################### tell Emacs this is a -*- makefile-gmake -*-
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#
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# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
# and/or sell copies of the Software, and to permit persons to whom the
|
||||
# Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
# DEALINGS IN THE SOFTWARE.
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||||
#
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# tmake for SW Mobile component makefile
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#
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###############################################################################
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NVGPU_UNIT_NAME=mm
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include $(NV_COMPONENT_DIR)/../../Makefile.units.common.interface.tmk
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# Local Variables:
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# indent-tabs-mode: t
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# tab-width: 8
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# End:
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# vi: set tabstop=8 noexpandtab:
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35
userspace/units/mm/mm/Makefile.tmk
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35
userspace/units/mm/mm/Makefile.tmk
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@@ -0,0 +1,35 @@
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################################### tell Emacs this is a -*- makefile-gmake -*-
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#
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# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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#
|
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# Permission is hereby granted, free of charge, to any person obtaining a
|
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# copy of this software and associated documentation files (the "Software"),
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# to deal in the Software without restriction, including without limitation
|
||||
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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# and/or sell copies of the Software, and to permit persons to whom the
|
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# Software is furnished to do so, subject to the following conditions:
|
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#
|
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# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
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# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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# DEALINGS IN THE SOFTWARE.
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#
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# tmake for SW Mobile component makefile
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#
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###############################################################################
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NVGPU_UNIT_NAME=mm
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include $(NV_COMPONENT_DIR)/../../Makefile.units.common.tmk
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# Local Variables:
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# indent-tabs-mode: t
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# tab-width: 8
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# End:
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# vi: set tabstop=8 noexpandtab:
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348
userspace/units/mm/mm/mm.c
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348
userspace/units/mm/mm/mm.c
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@@ -0,0 +1,348 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <unit/io.h>
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#include <unit/unit.h>
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#include <unit/core.h>
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#include <nvgpu/posix/io.h>
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#include "os/posix/os_posix.h"
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#include "hal/mm/mm_gp10b.h"
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#include "hal/mm/mm_gv11b.h"
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#include "hal/mm/cache/flush_gk20a.h"
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#include "hal/mm/cache/flush_gv11b.h"
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#include "hal/mm/gmmu/gmmu_gp10b.h"
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#include "hal/mm/gmmu/gmmu_gv11b.h"
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#include "hal/mm/mmu_fault/mmu_fault_gv11b.h"
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#include "hal/fb/fb_gm20b.h"
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#include "hal/fb/fb_gv11b.h"
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#include "hal/fb/fb_mmu_fault_gv11b.h"
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#include "hal/fb/intr/fb_intr_gv11b.h"
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#include "hal/fifo/ramin_gk20a.h"
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#include "hal/fifo/ramin_gp10b.h"
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#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
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#include <nvgpu/hw/gv11b/hw_flush_gv11b.h>
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#define TEST_ADDRESS 0x10002000
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struct unit_module *current_module;
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bool test_flag;
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/*
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* Write callback (for all nvgpu_writel calls).
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*/
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static void writel_access_reg_fn(struct gk20a *g,
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struct nvgpu_reg_access *access)
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{
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if (access->addr == flush_fb_flush_r()) {
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if (access->value == flush_fb_flush_pending_busy_v()) {
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unit_info(current_module,
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"writel: setting FB_flush to not pending\n");
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access->value = 0;
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}
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} else if (access->addr == flush_l2_flush_dirty_r()) {
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if (access->value == flush_l2_flush_dirty_pending_busy_v()) {
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unit_info(current_module,
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"writel: setting L2_flush to not pending\n");
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access->value = 0;
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}
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}
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nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
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nvgpu_posix_io_record_access(g, access);
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}
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/*
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* Read callback, similar to the write callback above.
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*/
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static void readl_access_reg_fn(struct gk20a *g,
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struct nvgpu_reg_access *access)
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{
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access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
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}
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/*
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* Define all the callbacks to be used during the test. Typically all
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* write operations use the same callback, likewise for all read operations.
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*/
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static struct nvgpu_posix_io_callbacks mmu_faults_callbacks = {
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/* Write APIs all can use the same accessor. */
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.writel = writel_access_reg_fn,
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.writel_check = writel_access_reg_fn,
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.bar1_writel = writel_access_reg_fn,
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.usermode_writel = writel_access_reg_fn,
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/* Likewise for the read APIs. */
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.__readl = readl_access_reg_fn,
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.readl = readl_access_reg_fn,
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.bar1_readl = readl_access_reg_fn,
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};
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static void init_platform(struct unit_module *m, struct gk20a *g, bool is_iGPU)
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{
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if (is_iGPU) {
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nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
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} else {
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nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, false);
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}
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/* Enable extra features to increase line coverage */
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nvgpu_set_enabled(g, NVGPU_SUPPORT_SEC2_VM, true);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_GSP_VM, true);
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}
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/*
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* Init the minimum set of HALs to use DMA amd GMMU features, then call the
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* init_mm base function.
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*/
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static int init_mm(struct unit_module *m, struct gk20a *g)
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{
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int err;
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struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
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p->mm_is_iommuable = true;
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g->ops.mm.gmmu.get_default_big_page_size =
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gp10b_mm_get_default_big_page_size;
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g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
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g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
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g->ops.mm.gmmu.map = nvgpu_gmmu_map_locked;
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g->ops.mm.gmmu.unmap = nvgpu_gmmu_unmap_locked;
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g->ops.mm.gmmu.gpu_phys_addr = gv11b_gpu_phys_addr;
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g->ops.mm.is_bar1_supported = gv11b_mm_is_bar1_supported;
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g->ops.mm.cache.l2_flush = gv11b_mm_l2_flush;
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g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush;
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#ifdef CONFIG_NVGPU_DGPU
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g->ops.fb.compression_page_size = gp10b_fb_compression_page_size;
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#endif
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g->ops.fb.tlb_invalidate = gm20b_fb_tlb_invalidate;
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g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
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g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
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g->ops.fb.is_fault_buf_enabled = gv11b_fb_is_fault_buf_enabled;
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g->ops.fb.read_mmu_fault_buffer_size =
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gv11b_fb_read_mmu_fault_buffer_size;
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g->ops.fb.init_hw = gv11b_fb_init_hw;
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g->ops.fb.intr.enable = gv11b_fb_intr_enable;
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nvgpu_posix_register_io(g, &mmu_faults_callbacks);
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nvgpu_posix_io_init_reg_space(g);
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/* Register space: FB_MMU */
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if (nvgpu_posix_io_add_reg_space(g, fb_niso_intr_r(), 0x800) != 0) {
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unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n");
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}
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/* Register space: HW_FLUSH */
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if (nvgpu_posix_io_add_reg_space(g, flush_fb_flush_r(), 0x20) != 0) {
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unit_return_fail(m, "nvgpu_posix_io_add_reg_space failed\n");
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}
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if (g->ops.mm.is_bar1_supported(g)) {
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unit_return_fail(m, "BAR1 is not supported on Volta+\n");
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}
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g->has_cde = true;
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err = nvgpu_init_mm_support(g);
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if (err != 0) {
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unit_return_fail(m, "nvgpu_init_mm_support failed err=%d\n",
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err);
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}
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err = nvgpu_mm_setup_hw(g);
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if (err != 0) {
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unit_return_fail(m, "nvgpu_mm_setup_hw failed err=%d\n",
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err);
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}
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return UNIT_SUCCESS;
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}
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/*
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* Test: test_mm_mm_init
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* This test must be run once and be the first one as it initializes the MM
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* subsystem.
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*/
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static int test_mm_init(struct unit_module *m, struct gk20a *g, void *args)
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{
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g->log_mask = 0;
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if (verbose_lvl(m) >= 1) {
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g->log_mask = gpu_dbg_map;
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}
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if (verbose_lvl(m) >= 2) {
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g->log_mask |= gpu_dbg_map_v;
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}
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if (verbose_lvl(m) >= 3) {
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g->log_mask |= gpu_dbg_pte;
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}
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current_module = m;
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init_platform(m, g, true);
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if (init_mm(m, g) != 0) {
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unit_return_fail(m, "nvgpu_init_mm_support failed\n");
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}
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return UNIT_SUCCESS;
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}
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/*
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* Test: test_mm_suspend
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* Test nvgpu_mm_suspend and run through some branches depending on enabled
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* HALs.
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*/
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static int test_mm_suspend(struct unit_module *m, struct gk20a *g,
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void *args)
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{
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int err;
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g->power_on = false;
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err = nvgpu_mm_suspend(g);
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if (err != -ETIMEDOUT) {
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unit_return_fail(m, "suspend did not fail as expected err=%d\n",
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err);
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}
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g->power_on = true;
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err = nvgpu_mm_suspend(g);
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if (err != 0) {
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unit_return_fail(m, "suspend fail err=%d\n", err);
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}
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/*
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* Some optional HALs are executed if not NULL in nvgpu_mm_suspend.
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* Calls above went through branches where these HAL pointers were NULL,
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* now define them and run again for complete coverage.
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*/
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g->ops.fb.intr.disable = gv11b_fb_intr_disable;
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g->ops.mm.mmu_fault.disable_hw = gv11b_mm_mmu_fault_disable_hw;
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g->power_on = true;
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err = nvgpu_mm_suspend(g);
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if (err != 0) {
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unit_return_fail(m, "suspend fail err=%d\n", err);
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}
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return UNIT_SUCCESS;
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}
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/*
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* Simple helper to toggle a flag when called.
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*/
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static void helper_deinit_pdb_cache_war(struct gk20a *g)
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{
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test_flag = true;
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}
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/*
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* Test: test_mm_remove_mm_support
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* Test mm.remove_support and run through some branches depending on enabled
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* HALs.
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*/
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static int test_mm_remove_mm_support(struct unit_module *m, struct gk20a *g,
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void *args)
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{
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/* Add BAR2 to have more VMs to free */
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g->ops.mm.init_bar2_vm = gp10b_mm_init_bar2_vm;
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g->ops.mm.init_bar2_vm(g);
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/*
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* Since the last step of the removal is to call
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* g->ops.ramin.deinit_pdb_cache_war, it is a good indication that
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* the removal completed successfully.
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*/
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g->ops.ramin.deinit_pdb_cache_war = helper_deinit_pdb_cache_war;
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test_flag = false;
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g->mm.remove_support(&g->mm);
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g->ops.ramin.deinit_pdb_cache_war = NULL;
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if (!test_flag) {
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unit_return_fail(m, "mm removal did not complete\n");
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}
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/* Add extra HALs to cover some branches */
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g->ops.mm.mmu_fault.info_mem_destroy =
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gv11b_mm_mmu_fault_info_mem_destroy;
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g->ops.mm.remove_bar2_vm = gp10b_mm_remove_bar2_vm;
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g->mm.remove_support(&g->mm);
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return UNIT_SUCCESS;
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}
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/*
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* Test: test_mm_page_sizes
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* Test a couple of page_size related functions
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*/
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static int test_mm_page_sizes(struct unit_module *m, struct gk20a *g,
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void *args)
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{
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if (nvgpu_mm_get_default_big_page_size(g) != SZ_64K) {
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unit_return_fail(m, "unexpected big page size (1)\n");
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}
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if (nvgpu_mm_get_available_big_page_sizes(g) != SZ_64K) {
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unit_return_fail(m, "unexpected big page size (2)\n");
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}
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/* For branch/line coverage */
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g->mm.disable_bigpage = true;
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if (nvgpu_mm_get_available_big_page_sizes(g) != 0) {
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unit_return_fail(m, "unexpected big page size (3)\n");
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}
|
||||
g->mm.disable_bigpage = false;
|
||||
|
||||
return UNIT_SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Test: test_mm_inst_block
|
||||
* Test nvgpu_inst_block_ptr.
|
||||
*/
|
||||
static int test_mm_inst_block(struct unit_module *m, struct gk20a *g,
|
||||
void *args)
|
||||
{
|
||||
u32 addr;
|
||||
struct nvgpu_mem *block = malloc(sizeof(struct nvgpu_mem));
|
||||
|
||||
block->aperture = APERTURE_SYSMEM;
|
||||
block->cpu_va = (void *) TEST_ADDRESS;
|
||||
|
||||
g->ops.ramin.base_shift = gk20a_ramin_base_shift;
|
||||
addr = nvgpu_inst_block_ptr(g, block);
|
||||
free(block);
|
||||
|
||||
if (addr != ((u32) TEST_ADDRESS >> g->ops.ramin.base_shift())) {
|
||||
unit_return_fail(m, "invalid inst_block_ptr address\n");
|
||||
}
|
||||
|
||||
return UNIT_SUCCESS;
|
||||
}
|
||||
|
||||
struct unit_module_test nvgpu_mm_mm_tests[] = {
|
||||
UNIT_TEST(init, test_mm_init, NULL, 0),
|
||||
UNIT_TEST(suspend, test_mm_suspend, NULL, 0),
|
||||
UNIT_TEST(remove_support, test_mm_remove_mm_support, NULL, 0),
|
||||
UNIT_TEST(page_sizes, test_mm_page_sizes, NULL, 0),
|
||||
UNIT_TEST(inst_block, test_mm_inst_block, NULL, 0),
|
||||
};
|
||||
|
||||
UNIT_MODULE(mm.mm, nvgpu_mm_mm_tests, UNIT_PRIO_NVGPU_TEST);
|
||||
Reference in New Issue
Block a user