From 699c2a15fa6340d0d27b275325d676904401c0a8 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Mon, 4 Feb 2019 10:54:55 -0500 Subject: [PATCH] gpu: nvgpu: pmgr: update type for size param Update interfaces to use size_t to align with boardobj_construct_super() and avoid unnecessary casts. JIRA NVGPU-1008 Change-Id: I7bff681f04f43e2f599d6f47138b04b2a94bfff3 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2011436 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-misra-checker Reviewed-by: Scott Long GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c | 4 ++-- drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c | 4 ++-- drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c index 31188b036..739ce727d 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c +++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c @@ -92,7 +92,7 @@ done: } static struct boardobj *construct_pwr_device(struct gk20a *g, - void *pargs, u16 pargs_size, u8 type) + void *pargs, size_t pargs_size, u8 type) { struct boardobj *board_obj_ptr = NULL; int status; @@ -142,7 +142,7 @@ static int devinit_get_pwr_device_table(struct gk20a *g, struct pwr_sensors_2x_entry pwr_sensor_table_entry = { 0 }; u32 index; u32 obj_index = 0; - u16 pwr_device_size; + size_t pwr_device_size; union { struct boardobj boardobj; struct pwr_device pwrdev; diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c index 97ec3f42e..d463895d7 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c +++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.c @@ -145,7 +145,7 @@ done: } static struct boardobj *construct_pwr_topology(struct gk20a *g, - void *pargs, u16 pargs_size, u8 type) + void *pargs, size_t pargs_size, u8 type) { struct boardobj *board_obj_ptr = NULL; int status; @@ -190,7 +190,7 @@ static int devinit_get_pwr_topology_table(struct gk20a *g, struct pwr_topology_2x_entry pwr_topology_table_entry = { 0 }; u32 index; u32 obj_index = 0; - u16 pwr_topology_size; + size_t pwr_topology_size; union { struct boardobj boardobj; struct pwr_channel pwrchannel; diff --git a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c index d1ede130f..26284a08e 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c +++ b/drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -256,7 +256,7 @@ done: } static struct boardobj *construct_pwr_policy(struct gk20a *g, - void *pargs, u16 pargs_size, u8 type) + void *pargs, size_t pargs_size, u8 type) { struct boardobj *board_obj_ptr = NULL; int status; @@ -372,7 +372,7 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g, static int _pwr_policy_construct_WAR_SW_Threshold_policy(struct gk20a *g, struct pmgr_pwr_policy *ppwrpolicyobjs, union pwr_policy_data_union *ppwrpolicydata, - u16 pwr_policy_size, + size_t pwr_policy_size, u32 obj_index) { int status = 0; @@ -528,7 +528,7 @@ static int devinit_get_pwr_policy_table(struct gk20a *g, struct pwr_policy_3x_header_unpacked hdr; u32 index; u32 obj_index = 0; - u16 pwr_policy_size; + size_t pwr_policy_size; bool integral_control = false; u32 hw_threshold_policy_index = 0; union pwr_policy_data_union pwr_policy_data;