gpu: nvgpu: vgpu: add basic t19x HALs

- Added t19x vgpu platform data
- Added basic vgpu HAL for gv11b.
- Added subctx header HAL.

Jira VFND-3796

Change-Id: I2b99364801b41d042b53e057f1a30e1194f354c3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master/r/1474729
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Richard Zhao
2017-04-10 15:32:59 -07:00
committed by mobile promotions
parent 7346122ae6
commit 6a25181882
11 changed files with 386 additions and 0 deletions

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@@ -21,3 +21,10 @@ nvgpu-y += \
nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o
nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += $(nvgpu-t19x)/common/linux/nvhost_t19x.o nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += $(nvgpu-t19x)/common/linux/nvhost_t19x.o
nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
$(nvgpu-t19x)/vgpu/gv11b/platform_gv11b_vgpu_tegra.o \
$(nvgpu-t19x)/vgpu/gv11b/vgpu_hal_gv11b.o \
$(nvgpu-t19x)/vgpu/gv11b/vgpu_gr_gv11b.o \
$(nvgpu-t19x)/vgpu/gv11b/vgpu_fifo_gv11b.o \
$(nvgpu-t19x)/vgpu/gv11b/vgpu_subctx_gv11b.o

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@@ -0,0 +1,80 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include "gk20a/gk20a.h"
#include "gk20a/hal_gk20a.h"
#include "gk20a/platform_gk20a.h"
#include "vgpu/clk_vgpu.h"
#include <nvgpu/nvhost.h>
#include <linux/platform_device.h>
static int gv11b_vgpu_probe(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct gk20a_platform *platform = dev_get_drvdata(dev);
struct resource *r;
void __iomem *regs;
struct fifo_gk20a *f = &platform->g->fifo;
int ret;
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usermode");
if (!r) {
dev_err(dev, "failed to get usermode regs\n");
return -ENXIO;
}
regs = devm_ioremap_resource(dev, r);
if (IS_ERR(regs)) {
dev_err(dev, "failed to map usermode regs\n");
return PTR_ERR(regs);
}
f->t19x.usermode_regs = regs;
#ifdef CONFIG_TEGRA_GK20A_NVHOST
ret = nvgpu_get_nvhost_dev(platform->g);
if (ret) {
f->t19x.usermode_regs = NULL;
return ret;
}
#endif
vgpu_init_clk_support(platform->g);
return 0;
}
struct gk20a_platform gv11b_vgpu_tegra_platform = {
.has_syncpoints = false,
.aggressive_sync_destroy_thresh = 64,
/* power management configuration */
.can_railgate_init = false,
.can_elpg_init = false,
.enable_slcg = false,
.enable_blcg = false,
.enable_elcg = false,
.enable_elpg = false,
.enable_aelpg = false,
.ch_wdt_timeout_ms = 5000,
.probe = gv11b_vgpu_probe,
.default_big_page_size = SZ_64K,
.clk_round_rate = vgpu_clk_round_rate,
.get_clk_freqs = vgpu_clk_get_freqs,
/* frequency scaling configuration */
.devfreq_governor = "userspace",
.virtual_dev = true,
};

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@@ -0,0 +1,26 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <gk20a/gk20a.h>
#include <vgpu/gp10b/vgpu_fifo_gp10b.h>
#include "vgpu_fifo_gv11b.h"
#include "vgpu_subctx_gv11b.h"
void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops)
{
vgpu_gp10b_init_fifo_ops(gops);
gops->fifo.init_fifo_setup_hw = NULL;
gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header;
}

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@@ -0,0 +1,21 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _VGPU_FIFO_GV11B_H_
#define _VGPU_FIFO_GV11B_H_
struct gpu_ops;
void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops);
#endif

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@@ -0,0 +1,40 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <gk20a/gk20a.h>
#include <vgpu/gr_vgpu.h>
#include <vgpu/gp10b/vgpu_gr_gp10b.h>
#include "vgpu_gr_gv11b.h"
#include "vgpu_subctx_gv11b.h"
static int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
{
int err;
err = vgpu_gv11b_alloc_subctx_header(c);
if (err)
return err;
err = vgpu_gr_commit_inst(c, gpu_va);
if (err)
vgpu_gv11b_free_subctx_header(c);
return err;
}
void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops)
{
vgpu_gp10b_init_gr_ops(gops);
gops->gr.commit_inst = vgpu_gr_gv11b_commit_inst;
}

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@@ -0,0 +1,19 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _VGPU_GR_GV11B_H_
#define _VGPU_GR_GV11B_H_
void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops);
#endif

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@@ -0,0 +1,40 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <gk20a/gk20a.h>
#include <gv11b/hal_gv11b.h>
#include <vgpu/vgpu.h>
#include <vgpu/vgpu_t19x.h>
#include <vgpu/gp10b/vgpu_mm_gp10b.h>
#include "vgpu_gr_gv11b.h"
#include "vgpu_fifo_gv11b.h"
int vgpu_gv11b_init_hal(struct gk20a *g)
{
int err;
gk20a_dbg_fn("");
err = gv11b_init_hal(g);
if (err)
return err;
vgpu_init_hal_common(g);
vgpu_gp10b_init_mm_ops(&g->ops);
vgpu_gv11b_init_gr_ops(&g->ops);
vgpu_gv11b_init_fifo_ops(&g->ops);
return 0;
}

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@@ -0,0 +1,70 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <gk20a/gk20a.h>
#include <vgpu/vgpu.h>
#include <linux/tegra_vgpu.h>
int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
{
struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_alloc_ctx_header_params *p =
&msg.params.t19x.alloc_ctx_header;
struct gr_gk20a *gr = &c->g->gr;
int err;
msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER;
msg.handle = vgpu_get_handle(c->g);
p->ch_handle = c->virt_ctx;
p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm,
gr->ctx_vars.golden_image_size,
gmmu_page_size_kernel);
if (!p->ctx_header_va) {
nvgpu_err(c->g, "alloc va failed for ctx_header");
return -ENOMEM;
}
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret;
if (unlikely(err)) {
nvgpu_err(c->g, "alloc ctx_header failed err %d", err);
__nvgpu_vm_free_va(c->vm, p->ctx_header_va,
gmmu_page_size_kernel);
return err;
}
ctx->mem.gpu_va = p->ctx_header_va;
return err;
}
void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
{
struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_free_ctx_header_params *p =
&msg.params.t19x.free_ctx_header;
int err;
if (ctx->mem.gpu_va) {
msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER;
msg.handle = vgpu_get_handle(c->g);
p->ch_handle = c->virt_ctx;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret;
if (unlikely(err))
nvgpu_err(c->g, "free ctx_header failed err %d", err);
__nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va,
gmmu_page_size_kernel);
ctx->mem.gpu_va = 0;
}
}

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@@ -0,0 +1,22 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _VGPU_SUBCTX_GV11B_H_
#define _VGPU_SUBCTX_GV11B_H_
struct channel_gk20a;
int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c);
void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c);
#endif

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@@ -0,0 +1,27 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef _VGPU_T19X_H_
#define _VGPU_T19X_H_
struct gk20a;
int vgpu_gv11b_init_hal(struct gk20a *g);
#define vgpu_t19x_init_hal(g) vgpu_gv11b_init_hal(g)
#define TEGRA_19x_VGPU_COMPAT_TEGRA "nvidia,gv11b-vgpu"
extern struct gk20a_platform gv11b_vgpu_tegra_platform;
#define t19x_vgpu_tegra_platform gv11b_vgpu_tegra_platform
#endif

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@@ -0,0 +1,34 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#ifndef __TEGRA_VGPU_T19X_H
#define __TEGRA_VGPU_T19X_H
#define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100
#define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101
struct tegra_vgpu_alloc_ctx_header_params {
u64 ch_handle;
u64 ctx_header_va;
};
struct tegra_vgpu_free_ctx_header_params {
u64 ch_handle;
};
union tegra_vgpu_t19x_params {
struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header;
struct tegra_vgpu_free_ctx_header_params free_ctx_header;
};
#endif