diff --git a/drivers/gpu/nvgpu/common/gr/fs_state.c b/drivers/gpu/nvgpu/common/gr/fs_state.c
index cd810d1b4..db38f24a1 100644
--- a/drivers/gpu/nvgpu/common/gr/fs_state.c
+++ b/drivers/gpu/nvgpu/common/gr/fs_state.c
@@ -73,19 +73,21 @@ static void gr_load_tpc_mask(struct gk20a *g, struct nvgpu_gr_config *config)
 	nvgpu_log_info(g, "pes_tpc_mask %u\n", pes_tpc_mask);
 
 #ifdef CONFIG_NVGPU_NON_FUSA
-	fuse_tpc_mask = g->ops.gr.config.get_gpc_tpc_mask(g, config, 0);
-	if ((g->tpc_fs_mask_user != 0U) &&
-				(g->tpc_fs_mask_user != fuse_tpc_mask)) {
-		if (fuse_tpc_mask == nvgpu_safe_sub_u32(BIT32(max_tpc_count),
-								U32(1))) {
-			val = g->tpc_fs_mask_user;
-			val &= nvgpu_safe_sub_u32(BIT32(max_tpc_count), U32(1));
-			/*
-			 * skip tpc to disable the other tpc cause channel
-			 * timeout
-			 */
-			val = nvgpu_safe_sub_u32(BIT32(hweight32(val)), U32(1));
-			pes_tpc_mask = val;
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		fuse_tpc_mask = g->ops.gr.config.get_gpc_tpc_mask(g, config, 0);
+		if ((g->tpc_fs_mask_user != 0U) &&
+					(g->tpc_fs_mask_user != fuse_tpc_mask)) {
+			if (fuse_tpc_mask == nvgpu_safe_sub_u32(BIT32(max_tpc_count),
+									U32(1))) {
+				val = g->tpc_fs_mask_user;
+				val &= nvgpu_safe_sub_u32(BIT32(max_tpc_count), U32(1));
+				/*
+				 * skip tpc to disable the other tpc cause channel
+				 * timeout
+				 */
+				val = nvgpu_safe_sub_u32(BIT32(hweight32(val)), U32(1));
+				pes_tpc_mask = val;
+			}
 		}
 	}
 #endif
@@ -130,8 +132,10 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
 	g->ops.gr.init.pd_tpc_per_gpc(g, config);
 
 #ifdef CONFIG_NVGPU_GRAPHICS
-	/* gr__setup_pd_mapping */
-	g->ops.gr.init.rop_mapping(g, config);
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		/* gr__setup_pd_mapping */
+		g->ops.gr.init.rop_mapping(g, config);
+	}
 #endif
 
 	g->ops.gr.init.pd_skip_table_gpc(g, config);
@@ -140,15 +144,17 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
 	tpc_cnt = nvgpu_gr_config_get_tpc_count(config);
 
 #ifdef CONFIG_NVGPU_NON_FUSA
-	fuse_tpc_mask = g->ops.gr.config.get_gpc_tpc_mask(g, config, 0);
-	max_tpc_cnt = nvgpu_gr_config_get_max_tpc_count(config);
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		fuse_tpc_mask = g->ops.gr.config.get_gpc_tpc_mask(g, config, 0);
+		max_tpc_cnt = nvgpu_gr_config_get_max_tpc_count(config);
 
-	if ((g->tpc_fs_mask_user != 0U) &&
-		(fuse_tpc_mask ==
-			nvgpu_safe_sub_u32(BIT32(max_tpc_cnt), U32(1)))) {
-		u32 val = g->tpc_fs_mask_user;
-		val &= nvgpu_safe_sub_u32(BIT32(max_tpc_cnt), U32(1));
-		tpc_cnt = (u32)hweight32(val);
+		if ((g->tpc_fs_mask_user != 0U) &&
+			(fuse_tpc_mask ==
+				nvgpu_safe_sub_u32(BIT32(max_tpc_cnt), U32(1)))) {
+			u32 val = g->tpc_fs_mask_user;
+			val &= nvgpu_safe_sub_u32(BIT32(max_tpc_cnt), U32(1));
+			tpc_cnt = (u32)hweight32(val);
+		}
 	}
 #endif
 
diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index 01050dc60..6f5116bac 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -251,16 +251,23 @@ static int gr_init_setup_hw(struct gk20a *g, struct nvgpu_gr *gr)
 	}
 
 #ifdef CONFIG_NVGPU_GRAPHICS
-	err = nvgpu_gr_zcull_init_hw(g, gr->zcull, gr->config);
-	if (err != 0) {
-		goto out;
-	}
-#endif /* CONFIG_NVGPU_GRAPHICS */
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		err = nvgpu_gr_zcull_init_hw(g, gr->zcull, gr->config);
+		if (err != 0) {
+			goto out;
+		}
 
-#ifdef CONFIG_NVGPU_GRAPHICS
-	err = nvgpu_gr_zbc_load_table(g, gr->zbc);
-	if (err != 0) {
-		goto out;
+		err = nvgpu_gr_zbc_load_table(g, gr->zbc);
+		if (err != 0) {
+			goto out;
+		}
+
+		if (g->ops.gr.init.preemption_state != NULL) {
+			err = g->ops.gr.init.preemption_state(g);
+			if (err != 0) {
+				goto out;
+			}
+		}
 	}
 #endif /* CONFIG_NVGPU_GRAPHICS */
 
@@ -274,15 +281,6 @@ static int gr_init_setup_hw(struct gk20a *g, struct nvgpu_gr *gr)
 		g->ops.gr.init.lg_coalesce(g, 0);
 	}
 
-#ifdef CONFIG_NVGPU_GRAPHICS
-	if (g->ops.gr.init.preemption_state != NULL) {
-		err = g->ops.gr.init.preemption_state(g);
-		if (err != 0) {
-			goto out;
-		}
-	}
-#endif
-
 	/* floorsweep anything left */
 	err = nvgpu_gr_fs_state_init(g, gr->config);
 	if (err != 0) {
@@ -488,29 +486,29 @@ static int gr_init_setup_sw(struct gk20a *g, struct nvgpu_gr *gr)
 	}
 #endif
 
-#ifdef CONFIG_NVGPU_GRAPHICS
-	err = nvgpu_gr_config_init_map_tiles(g, gr->config);
-	if (err != 0) {
-		goto clean_up;
-	}
-
-	err = nvgpu_gr_zcull_init(g, &gr->zcull,
-			nvgpu_gr_falcon_get_zcull_image_size(gr->falcon),
-			gr->config);
-	if (err != 0) {
-		goto clean_up;
-	}
-#endif /* CONFIG_NVGPU_GRAPHICS */
-
 	err = gr_init_ctx_bufs(g, gr);
 	if (err != 0) {
 		goto clean_up;
 	}
 
 #ifdef CONFIG_NVGPU_GRAPHICS
-	err = nvgpu_gr_zbc_init(g, &gr->zbc);
-	if (err != 0) {
-		goto clean_up;
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		err = nvgpu_gr_config_init_map_tiles(g, gr->config);
+		if (err != 0) {
+			goto clean_up;
+		}
+
+		err = nvgpu_gr_zcull_init(g, &gr->zcull,
+				nvgpu_gr_falcon_get_zcull_image_size(gr->falcon),
+				gr->config);
+		if (err != 0) {
+			goto clean_up;
+		}
+
+		err = nvgpu_gr_zbc_init(g, &gr->zbc);
+		if (err != 0) {
+			goto clean_up;
+		}
 	}
 #endif /* CONFIG_NVGPU_GRAPHICS */
 
diff --git a/drivers/gpu/nvgpu/common/gr/gr_config.c b/drivers/gpu/nvgpu/common/gr/gr_config.c
index 7d714ee1d..b4ab011c3 100644
--- a/drivers/gpu/nvgpu/common/gr/gr_config.c
+++ b/drivers/gpu/nvgpu/common/gr/gr_config.c
@@ -234,10 +234,12 @@ static bool gr_config_alloc_struct_mem(struct gk20a *g,
 	gpc_size = nvgpu_safe_mult_u64((size_t)config->gpc_count, sizeof(u32));
 	config->gpc_tpc_count = nvgpu_kzalloc(g, gpc_size);
 #ifdef CONFIG_NVGPU_GRAPHICS
-	config->max_zcull_per_gpc_count = nvgpu_get_litter_value(g,
-		GPU_LIT_NUM_ZCULL_BANKS);
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		config->max_zcull_per_gpc_count = nvgpu_get_litter_value(g,
+			GPU_LIT_NUM_ZCULL_BANKS);
 
-	config->gpc_zcb_count = nvgpu_kzalloc(g, gpc_size);
+		config->gpc_zcb_count = nvgpu_kzalloc(g, gpc_size);
+	}
 #endif
 	config->gpc_ppc_count = nvgpu_kzalloc(g, gpc_size);
 
@@ -403,11 +405,13 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g)
 					config->gpc_tpc_count[gpc_index]);
 
 #ifdef CONFIG_NVGPU_GRAPHICS
-		config->gpc_zcb_count[gpc_index] =
-			g->ops.gr.config.get_zcull_count_in_gpc(g, config,
-				gpc_index);
-		config->zcb_count = nvgpu_safe_add_u32(config->zcb_count,
-					config->gpc_zcb_count[gpc_index]);
+		if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+			config->gpc_zcb_count[gpc_index] =
+				g->ops.gr.config.get_zcull_count_in_gpc(g, config,
+					gpc_index);
+			config->zcb_count = nvgpu_safe_add_u32(config->zcb_count,
+						config->gpc_zcb_count[gpc_index]);
+		}
 #endif
 
 		gr_config_init_pes_tpc(g, config, gpc_index);
diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c
index 98e4991ae..07cdcdaec 100644
--- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b_fusa.c
@@ -576,13 +576,15 @@ defined(CONFIG_NVGPU_CTXSW_FW_ERROR_CODE_TESTING)
 #endif
 
 #ifdef CONFIG_NVGPU_GRAPHICS
-	ret = g->ops.gr.falcon.ctrl_ctxsw(g,
-		NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE,
-		0, &sizes->zcull_image_size);
-	if (ret != 0) {
-		nvgpu_err(g,
-			"query zcull ctx image size failed");
-		return ret;
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		ret = g->ops.gr.falcon.ctrl_ctxsw(g,
+			NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE,
+			0, &sizes->zcull_image_size);
+		if (ret != 0) {
+			nvgpu_err(g,
+				"query zcull ctx image size failed");
+			return ret;
+		}
 	}
 
 	nvgpu_log(g, gpu_dbg_gr, "ZCULL image size = %u", sizes->zcull_image_size);
diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b_fusa.c
index 3503e6f12..d58c1282b 100644
--- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gp10b_fusa.c
@@ -43,12 +43,14 @@ int gp10b_gr_falcon_init_ctx_state(struct gk20a *g,
 		return err;
 	}
 
-	err = g->ops.gr.falcon.ctrl_ctxsw(g,
-		NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE, 0U,
-		&sizes->preempt_image_size);
-	if (err != 0) {
-		nvgpu_err(g, "query preempt image size failed");
-		return err;
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+		err = g->ops.gr.falcon.ctrl_ctxsw(g,
+			NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE, 0U,
+			&sizes->preempt_image_size);
+		if (err != 0) {
+			nvgpu_err(g, "query preempt image size failed");
+			return err;
+		}
 	}
 
 	nvgpu_log(g, gpu_dbg_gr, "Preempt image size = %u", sizes->preempt_image_size);
diff --git a/drivers/gpu/nvgpu/os/linux/driver_common.c b/drivers/gpu/nvgpu/os/linux/driver_common.c
index dd52a03ac..c6f549e2d 100644
--- a/drivers/gpu/nvgpu/os/linux/driver_common.c
+++ b/drivers/gpu/nvgpu/os/linux/driver_common.c
@@ -205,6 +205,9 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
 			nvgpu_platform_is_silicon(g) ? platform->enable_mscg : false;
 		g->can_elpg =
 			nvgpu_platform_is_silicon(g) ? platform->can_elpg_init : false;
+		if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
+			g->can_elpg = false;
+		}
 
 		nvgpu_set_enabled(g, NVGPU_PMU_PERFMON, platform->enable_perfmon);
 	}