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gpu: nvgpu: update sm ecc_status_error handling

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Use gv11b_gr_intr_handle_tpc_sm_ecc_exception
function for future chip to avoid code replication.

Add sm_ecc_status_errors hal to read
the ecc_status_errors

Jira NVGPU-5033

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: I4a25837d9b833a48307b9353b82ff6597f985e41
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325537
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2020-04-07 18:16:23 -07:00
committed by Alex Waterman
parent 72d01afd0c
commit 6a7bf6cdc0
5 changed files with 557 additions and 186 deletions
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6
drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
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@@ -45,6 +45,9 @@ struct nvgpu_fecs_ecc_status;
struct nvgpu_fecs_host_intr_status;
struct netlist_av_list;
struct nvgpu_hw_err_inject_info_desc;
struct nvgpu_gr_sm_ecc_status;
enum nvgpu_gr_sm_ecc_error_types;
#ifdef CONFIG_NVGPU_FECS_TRACE
struct nvgpu_gr_subctx;
@@ -504,6 +507,9 @@ struct gops_gr_intr {
u32 (*get_sm_no_lock_down_hww_global_esr_mask)(
struct gk20a *g);
u32 (*get_ctxsw_checksum_mismatch_mailbox_val)(void);
bool (*sm_ecc_status_errors)(struct gk20a *g, u32 ecc_status_reg,
enum nvgpu_gr_sm_ecc_error_types err_type,
struct nvgpu_gr_sm_ecc_status *ecc_status);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void (*handle_tex_exception)(struct gk20a *g,
u32 gpc, u32 tpc);