From 6acd7924c56031bfa4de7c37b9141fea9d1e9d7b Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 13 Jan 2020 15:33:30 +0530 Subject: [PATCH] gpu: nvgpu: unit: add UT for gops.gr.init.commit_global_bundle_cb Add a code coverage test for HAL function exposed by common.gr.init subunit : g->ops.gr.init.commit_global_bundle_cb Jira NVGPU-4778 Change-Id: Ibd8bd8513c63e6d5a6734a4ccc6744861de9e5e2 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279900 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- .../units/gr/init/nvgpu-gr-init-hal-gv11b.c | 22 +++++++++++++++++++ .../units/gr/init/nvgpu-gr-init-hal-gv11b.h | 8 ++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.c b/userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.c index 9ba44a13e..78d742c92 100644 --- a/userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.c +++ b/userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.c @@ -777,6 +777,11 @@ fail: return ret; } +static u32 test_gr_get_min_gpm_fifo_depth(struct gk20a *g) +{ + return 0; +} + int test_gr_init_hal_error_injection(struct unit_module *m, struct gk20a *g, void *args) { @@ -785,6 +790,7 @@ int test_gr_init_hal_error_injection(struct unit_module *m, struct nvgpu_gr_ctx_desc *desc; struct nvgpu_gr_ctx *gr_ctx = NULL; u32 size; + struct gpu_ops gops = g->ops; g->ops.mm.cache.l2_flush = dummy_l2_flush; @@ -836,6 +842,22 @@ int test_gr_init_hal_error_injection(struct unit_module *m, EXPECT_BUG(g->ops.gr.init.get_attrib_cb_size(g, 0)); EXPECT_BUG(g->ops.gr.init.get_alpha_cb_size(g, 0)); + /* + * Make g->ops.gr.init.get_min_gpm_fifo_depth return zero, so that + * we choose data as 0 in gp10b_gr_init_commit_global_bundle_cb() + * and program it. + * Ensure that 0 was programmed in corresponding field in + * register gr_pd_ab_dist_cfg2_r() by reading it back. + */ + g->ops.gr.init.get_min_gpm_fifo_depth = test_gr_get_min_gpm_fifo_depth; + g->ops.gr.init.commit_global_bundle_cb(g, gr_ctx, 0xffff, 0xffff, false); + if (nvgpu_readl(g, gr_pd_ab_dist_cfg2_r()) != + g->ops.gr.init.get_bundle_cb_token_limit(g)) { + unit_return_fail(m, "expected value not set"); + } + + g->ops = gops; + /* cleanup */ nvgpu_gr_ctx_free_patch_ctx(g, vm, gr_ctx); nvgpu_free_gr_ctx_struct(g, gr_ctx); diff --git a/userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.h b/userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.h index 99f440d0f..8e6fa54dc 100644 --- a/userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.h +++ b/userspace/units/gr/init/nvgpu-gr-init-hal-gv11b.h @@ -261,7 +261,9 @@ int test_gr_init_hal_config_error_injection(struct unit_module *m, * gops_gr_init.get_attrib_cb_size, * gv11b_gr_init_get_attrib_cb_size, * gops_gr_init.get_alpha_cb_size, - * gv11b_gr_init_get_alpha_cb_size + * gv11b_gr_init_get_alpha_cb_size, + * gops_gr_init.commit_global_bundle_cb, + * gp10b_gr_init_commit_global_bundle_cb * * Input: gr_init_setup, gr_init_prepare, gr_init_support must have * been executed successfully. @@ -275,6 +277,10 @@ int test_gr_init_hal_config_error_injection(struct unit_module *m, * - Call g->ops.gr.init.get_attrib_cb_size and g->ops.gr.init.get_alpha_cb_size * with tpc_count = 0 for code coverage. Ensure that a BUG() is triggered. * We are not interested in return value since tpc_count can never be 0. + * - Stub g->ops.gr.init.get_min_gpm_fifo_depth so that it returns 0. This will + * make g->ops.gr.init.commit_global_bundle_cb to write 0 in data field in + * register gr_pd_ab_dist_cfg2_r(). Verify same by reading back the register. + * - Restore all the gops operations. * - Cleanup temporary resources. * * Output: Returns PASS if the steps above were executed successfully. FAIL