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gpu: nvgpu: container_of() changes to ch sync code

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The container_of() macro used in nvgpu produces the following set
of MISRA required rule violations:

 * Rule 11.3 : A cast shall not be performed between a pointer to
               object type and a pointer to a different object to type.

 * Rule 11.8 : A cast shall not remove any const or volatile
               qualification from the type pointed to be a pointer.

 * Rule 20.7 : Expressions resulting from the expansion of macro
               parameters shall be enclosed in parentheses.

Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.

This patch uses that same equivalent implementation in two new
(static) functions that are used to replace references to
container_of() in common channel sync code:

 * nvgpu_channel_sync_semaphore_from_ops
 * nvgpu_channel_sync_syncpt_from_ops

It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.

JIRA NVGPU-782

Change-Id: Ib4279c7d28824ce5888838580a54b573323f7152
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993787
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Scott Long
2019-01-12 12:00:12 -08:00
committed by mobile promotions
parent 11e9e8fa49
commit 6b66428a34
2 changed files with 30 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/nvgpu/common/sync/channel_sync_syncpt.c
View File

@@ -1,7 +1,7 @@
/*
* GK20A Channel Synchronization Abstraction
*
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -47,6 +47,14 @@ struct nvgpu_channel_sync_syncpt {
struct nvgpu_mem syncpt_buf;
};
static struct nvgpu_channel_sync_syncpt *
nvgpu_channel_sync_syncpt_from_ops(struct nvgpu_channel_sync *ops)
{
return (struct nvgpu_channel_sync_syncpt *)
((uintptr_t)ops -
offsetof(struct nvgpu_channel_sync_syncpt, ops));
}
static int channel_sync_syncpt_gen_wait_cmd(struct channel_gk20a *c,
u32 id, u32 thresh, struct priv_cmd_entry *wait_cmd,
u32 wait_cmd_size, u32 pos, bool preallocated)
@@ -103,7 +111,7 @@ static int channel_sync_syncpt_wait_fd(struct nvgpu_channel_sync *s, int fd,
struct nvgpu_os_fence os_fence = {0};
struct nvgpu_os_fence_syncpt os_fence_syncpt = {0};
struct nvgpu_channel_sync_syncpt *sp =
container_of(s, struct nvgpu_channel_sync_syncpt, ops);
nvgpu_channel_sync_syncpt_from_ops(s);
struct channel_gk20a *c = sp->c;
int err = 0;
u32 i, num_fences, wait_cmd_size;
@@ -182,7 +190,7 @@ static int channel_sync_syncpt_incr_common(struct nvgpu_channel_sync *s,
u32 thresh;
int err;
struct nvgpu_channel_sync_syncpt *sp =
container_of(s, struct nvgpu_channel_sync_syncpt, ops);
nvgpu_channel_sync_syncpt_from_ops(s);
struct channel_gk20a *c = sp->c;
struct nvgpu_os_fence os_fence = {0};
@@ -287,14 +295,14 @@ static int channel_sync_syncpt_incr_user(struct nvgpu_channel_sync *s,
static void channel_sync_syncpt_set_min_eq_max(struct nvgpu_channel_sync *s)
{
struct nvgpu_channel_sync_syncpt *sp =
container_of(s, struct nvgpu_channel_sync_syncpt, ops);
nvgpu_channel_sync_syncpt_from_ops(s);
nvgpu_nvhost_syncpt_set_min_eq_max_ext(sp->nvhost_dev, sp->id);
}
static void channel_sync_syncpt_set_safe_state(struct nvgpu_channel_sync *s)
{
struct nvgpu_channel_sync_syncpt *sp =
container_of(s, struct nvgpu_channel_sync_syncpt, ops);
nvgpu_channel_sync_syncpt_from_ops(s);
nvgpu_nvhost_syncpt_set_safe_state(sp->nvhost_dev, sp->id);
}
@@ -311,7 +319,7 @@ static u64 channel_sync_syncpt_get_address(struct nvgpu_channel_sync_syncpt *sp)
static void channel_sync_syncpt_destroy(struct nvgpu_channel_sync *s)
{
struct nvgpu_channel_sync_syncpt *sp =
container_of(s, struct nvgpu_channel_sync_syncpt, ops);
nvgpu_channel_sync_syncpt_from_ops(s);
sp->c->g->ops.fifo.free_syncpt_buf(sp->c, &sp->syncpt_buf);
@@ -343,7 +351,7 @@ nvgpu_channel_sync_to_syncpt(struct nvgpu_channel_sync *sync)
struct nvgpu_channel_sync_syncpt *syncpt = NULL;
if (sync->wait_fence_fd == channel_sync_syncpt_wait_fd) {
syncpt = container_of(sync, struct nvgpu_channel_sync_syncpt, ops);
syncpt = nvgpu_channel_sync_syncpt_from_ops(sync);
}
return syncpt;