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gpu: nvgpu: vgpu: get virtual SMs mapping

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On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in
vgpu constants to properly dimension the virtual SM to TPC/GPC
mapping in virtualization case.
Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping.

Bug 2039676

Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631203
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2017-12-30 13:04:19 -08:00
committed by mobile promotions
parent 5fb7c7d8f9
commit 6b90684cee
13 changed files with 110 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -40,24 +40,3 @@ void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g)
#endif
}
int vgpu_gm20b_init_fs_state(struct gk20a *g)
{
struct gr_gk20a *gr = &g->gr;
u32 tpc_index, gpc_index;
u32 sm_id = 0;
gk20a_dbg_fn("");
for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
for (tpc_index = 0; tpc_index < gr->gpc_tpc_count[gpc_index];
tpc_index++) {
g->gr.sm_to_cluster[sm_id].tpc_index = tpc_index;
g->gr.sm_to_cluster[sm_id].gpc_index = gpc_index;
sm_id++;
}
}
gr->no_of_sm = sm_id;
return 0;
}

3
drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -20,6 +20,5 @@
#include "gk20a/gk20a.h"
void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g);
int vgpu_gm20b_init_fs_state(struct gk20a *g);
#endif

6
drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -92,7 +92,7 @@ static const struct gpu_ops vgpu_gm20b_ops = {
.is_valid_compute_class = gr_gm20b_is_valid_compute_class,
.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = vgpu_gm20b_init_fs_state,
.init_fs_state = vgpu_gr_init_fs_state,
.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
@@ -145,7 +145,7 @@ static const struct gpu_ops vgpu_gm20b_ops = {
.suspend_contexts = vgpu_gr_suspend_contexts,
.resume_contexts = vgpu_gr_resume_contexts,
.get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
.init_sm_id_table = gr_gk20a_init_sm_id_table,
.init_sm_id_table = vgpu_gr_init_sm_id_table,
.load_smid_config = gr_gm20b_load_smid_config,
.program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
.is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,

6
drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -106,7 +106,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.is_valid_compute_class = gr_gp10b_is_valid_compute_class,
.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = vgpu_gm20b_init_fs_state,
.init_fs_state = vgpu_gr_init_fs_state,
.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
@@ -159,7 +159,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.suspend_contexts = vgpu_gr_suspend_contexts,
.resume_contexts = vgpu_gr_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.init_sm_id_table = gr_gk20a_init_sm_id_table,
.init_sm_id_table = vgpu_gr_init_sm_id_table,
.load_smid_config = gr_gp10b_load_smid_config,
.program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
.is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,

65
drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
View File

@@ -1,7 +1,7 @@
/*
* Virtualized GPU Graphics
*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -610,6 +610,7 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
{
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
u32 gpc_index;
u32 sm_per_tpc;
int err = -ENOMEM;
gk20a_dbg_fn("");
@@ -628,8 +629,10 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
if (!gr->gpc_tpc_mask)
goto cleanup;
sm_per_tpc = priv->constants.sm_per_tpc;
gr->sm_to_cluster = nvgpu_kzalloc(g, gr->gpc_count *
gr->max_tpc_per_gpc_count *
sm_per_tpc *
sizeof(struct sm_info));
if (!gr->sm_to_cluster)
goto cleanup;
@@ -1215,3 +1218,63 @@ void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
nvgpu_mutex_release(&g->dbg_sessions_lock);
}
int vgpu_gr_init_sm_id_table(struct gk20a *g)
{
struct tegra_vgpu_cmd_msg msg = {};
struct tegra_vgpu_vsms_mapping_params *p = &msg.params.vsms_mapping;
struct tegra_vgpu_vsms_mapping_entry *entry;
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
struct sm_info *sm_info;
int err;
struct gr_gk20a *gr = &g->gr;
size_t oob_size;
void *handle = NULL;
u32 sm_id;
u32 max_sm;
msg.cmd = TEGRA_VGPU_CMD_GET_VSMS_MAPPING;
msg.handle = vgpu_get_handle(g);
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
err = err ? err : msg.ret;
if (err) {
nvgpu_err(g, "get vsms mapping failed err %d", err);
return err;
}
handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT,
tegra_gr_comm_get_server_vmid(),
TEGRA_VGPU_QUEUE_CMD,
(void **)&entry, &oob_size);
if (!handle)
return -EINVAL;
max_sm = gr->gpc_count *
gr->max_tpc_per_gpc_count *
priv->constants.sm_per_tpc;
if (p->num_sm > max_sm)
return -EINVAL;
if ((p->num_sm * sizeof(*entry)) > oob_size)
return -EINVAL;
gr->no_of_sm = p->num_sm;
for (sm_id = 0; sm_id < p->num_sm; sm_id++, entry++) {
sm_info = &gr->sm_to_cluster[sm_id];
sm_info->tpc_index = entry->tpc_index;
sm_info->gpc_index = entry->gpc_index;
sm_info->sm_index = entry->sm_index;
sm_info->global_tpc_index = entry->global_tpc_index;
}
tegra_gr_comm_oob_put_ptr(handle);
return 0;
}
int vgpu_gr_init_fs_state(struct gk20a *g)
{
if (!g->ops.gr.init_sm_id_table)
return -EINVAL;
return g->ops.gr.init_sm_id_table(g);
}

4
drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -60,5 +60,7 @@ int vgpu_gr_resume_contexts(struct gk20a *g,
struct dbg_session_gk20a *dbg_s,
int *ctx_resident_ch_fd);
int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
int vgpu_gr_init_sm_id_table(struct gk20a *g);
int vgpu_gr_init_fs_state(struct gk20a *g);
#endif

6
drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -126,7 +126,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.is_valid_compute_class = gr_gv11b_is_valid_compute_class,
.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
.init_fs_state = vgpu_gm20b_init_fs_state,
.init_fs_state = vgpu_gr_init_fs_state,
.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
@@ -179,7 +179,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.suspend_contexts = vgpu_gr_suspend_contexts,
.resume_contexts = vgpu_gr_resume_contexts,
.get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
.init_sm_id_table = gr_gv100_init_sm_id_table,
.init_sm_id_table = vgpu_gr_init_sm_id_table,
.load_smid_config = gr_gv11b_load_smid_config,
.program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
.is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,

2
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -392,7 +392,7 @@ struct gpu_ops {
void (*update_boosted_ctx)(struct gk20a *g,
struct nvgpu_mem *mem,
struct gr_ctx_desc *gr_ctx);
void (*init_sm_id_table)(struct gk20a *g);
int (*init_sm_id_table)(struct gk20a *g);
int (*load_smid_config)(struct gk20a *g);
void (*program_sm_id_numbering)(struct gk20a *g,
u32 gpc, u32 tpc, u32 smid);

11
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1,7 +1,7 @@
/*
* GK20A Graphics
*
* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1137,7 +1137,7 @@ static inline u32 count_bits(u32 mask)
return count;
}
void gr_gk20a_init_sm_id_table(struct gk20a *g)
int gr_gk20a_init_sm_id_table(struct gk20a *g)
{
u32 gpc, tpc;
u32 sm_id = 0;
@@ -1156,6 +1156,7 @@ void gr_gk20a_init_sm_id_table(struct gk20a *g)
}
}
g->gr.no_of_sm = sm_id;
return 0;
}
/*
@@ -1178,11 +1179,15 @@ int gr_gk20a_init_fs_state(struct gk20a *g)
u32 tpc_per_gpc;
u32 fuse_tpc_mask;
u32 reg_index;
int err;
gk20a_dbg_fn("");
if (g->ops.gr.init_sm_id_table) {
g->ops.gr.init_sm_id_table(g);
err = g->ops.gr.init_sm_id_table(g);
if (err)
return err;
/* Is table empty ? */
if (g->gr.no_of_sm == 0)
return -EINVAL;

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -766,7 +766,7 @@ u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g);
int gr_gk20a_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c);
void gr_gk20a_init_sm_id_table(struct gk20a *g);
int gr_gk20a_init_sm_id_table(struct gk20a *g);
int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va);

8
drivers/gpu/nvgpu/gv100/gr_gv100.c
View File

@@ -1,7 +1,7 @@
/*
* GV100 GPU GR
*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -199,14 +199,14 @@ void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
{
}
void gr_gv100_init_sm_id_table(struct gk20a *g)
int gr_gv100_init_sm_id_table(struct gk20a *g)
{
u32 gpc, tpc, sm, pes, gtpc;
u32 sm_id = 0;
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
u32 num_sm = sm_per_tpc * g->gr.tpc_count;
int perf, maxperf;
int err;
int err = 0;
unsigned long *gpc_tpc_mask;
u32 *tpc_table, *gpc_table;
@@ -217,6 +217,7 @@ void gr_gv100_init_sm_id_table(struct gk20a *g)
if (!gpc_table || !tpc_table || !gpc_tpc_mask) {
nvgpu_err(g, "Error allocating memory for sm tables");
err = -ENOMEM;
goto exit_build_table;
}
@@ -273,6 +274,7 @@ exit_build_table:
nvgpu_kfree(g, gpc_table);
nvgpu_kfree(g, tpc_table);
nvgpu_kfree(g, gpc_tpc_mask);
return err;
}
void gr_gv100_load_tpc_mask(struct gk20a *g)

4
drivers/gpu/nvgpu/gv100/gr_gv100.h
View File

@@ -1,7 +1,7 @@
/*
* GV100 GPU GR
*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -28,7 +28,7 @@
void gr_gv100_bundle_cb_defaults(struct gk20a *g);
void gr_gv100_cb_size_default(struct gk20a *g);
void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
void gr_gv100_init_sm_id_table(struct gk20a *g);
int gr_gv100_init_sm_id_table(struct gk20a *g);
void gr_gv100_program_sm_id_numbering(struct gk20a *g,
u32 gpc, u32 tpc, u32 smid);
int gr_gv100_load_smid_config(struct gk20a *g);

16
include/linux/tegra_vgpu.h
View File

@@ -1,7 +1,7 @@
/*
* Tegra GPU Virtualization Interfaces to Server
*
* Copyright (c) 2014-2017, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2014-2018, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -111,6 +111,7 @@ enum {
TEGRA_VGPU_CMD_PERFBUF_MGT = 73,
TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74,
TEGRA_VGPU_CMD_TSG_RELEASE = 75,
TEGRA_VGPU_CMD_GET_VSMS_MAPPING = 76,
};
struct tegra_vgpu_connect_params {
@@ -482,6 +483,7 @@ struct tegra_vgpu_constants_params {
u32 channel_base;
struct tegra_vgpu_engines_info engines_info;
u32 num_pce;
u32 sm_per_tpc;
};
struct tegra_vgpu_channel_cyclestats_snapshot_params {
@@ -530,6 +532,17 @@ struct tegra_vgpu_get_gpu_freq_table_params {
u32 freqs[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; /* in kHz */
};
struct tegra_vgpu_vsms_mapping_params {
u32 num_sm;
};
struct tegra_vgpu_vsms_mapping_entry {
u32 gpc_index;
u32 tpc_index;
u32 sm_index;
u32 global_tpc_index;
};
struct tegra_vgpu_cmd_msg {
u32 cmd;
int ret;
@@ -584,6 +597,7 @@ struct tegra_vgpu_cmd_msg {
struct tegra_vgpu_perfbuf_mgt_params perfbuf_management;
struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper;
struct tegra_vgpu_get_gpu_freq_table_params get_gpu_freq_table;
struct tegra_vgpu_vsms_mapping_params vsms_mapping;
#ifdef CONFIG_TEGRA_19x_GPU
union tegra_vgpu_t19x_params t19x;
#endif