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gpu: nvgpu: move chip specific teardown_mask/unmask_intr

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Move chip specific functions for teardown_mask_intr and
teardown_unmask_intr to hal/fifo/fifo_intr_[chip].[ch]

Renamed
teardown_mask_intr -> intr_set_recover_mask
teardown_unmask_intr -> intr_unset_recover_mask

JIRA NVGPU-1314

Change-Id: If233565cbdb09d77cfebd4346edcc3fe64584355
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093980
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-04-09 22:20:19 -07:00
committed by mobile promotions
parent 59bf3919e2
commit 6ba1f5db3b
16 changed files with 73 additions and 73 deletions
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21
drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a.c
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@@ -290,3 +290,24 @@ bool gk20a_fifo_is_mmu_fault_pending(struct gk20a *g)
return false;
}
}
void gk20a_fifo_intr_set_recover_mask(struct gk20a *g)
{
u32 val;
val = nvgpu_readl(g, fifo_intr_en_0_r());
val &= ~(fifo_intr_en_0_sched_error_m() |
fifo_intr_en_0_mmu_fault_m());
nvgpu_writel(g, fifo_intr_en_0_r(), val);
nvgpu_writel(g, fifo_intr_0_r(), fifo_intr_0_sched_error_reset_f());
}
void gk20a_fifo_intr_unset_recover_mask(struct gk20a *g)
{
u32 val;
val = nvgpu_readl(g, fifo_intr_en_0_r());
val |= fifo_intr_en_0_mmu_fault_f(1) | fifo_intr_en_0_sched_error_f(1);
nvgpu_writel(g, fifo_intr_en_0_r(), val);
}