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gpu: nvgpu: remove redundant GR ops

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g->ops.gr.enable_cde_in_fecs and g->ops.gr.update_boosted_ctx
are no longer required since we can directly call
g->ops.gr.ctxsw_prog.set_cde_enabled and
g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies
respectively

remove those functions and the ops

Jira NVGPU-1526

Change-Id: Idb0ad5f634e78aac44ec325ba2b7f59c612b29e8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972184
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-12-13 16:38:04 +05:30
committed by mobile promotions
parent 7aac00ee58
commit 6bbcdb51c6
13 changed files with 13 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1746,8 +1746,8 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
g->ops.gr.ctxsw_prog.init_ctxsw_hdr_data(g, mem);
}
if ((g->ops.gr.enable_cde_in_fecs != NULL) && c->cde) {
g->ops.gr.enable_cde_in_fecs(g, mem);
if ((g->ops.gr.ctxsw_prog.set_cde_enabled != NULL) && c->cde) {
g->ops.gr.ctxsw_prog.set_cde_enabled(g, mem);
}
/* set priv access map */
@@ -1763,8 +1763,10 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
g->ops.gr.update_ctxsw_preemption_mode(g, gr_ctx, &c->ctx_header);
}
if (g->ops.gr.update_boosted_ctx != NULL) {
g->ops.gr.update_boosted_ctx(g, mem, gr_ctx);
if (g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies !=
NULL) {
g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies(g,
mem, gr_ctx->boosted_ctx);
}
nvgpu_log(g, gpu_dbg_info, "write patch count = %d",

5
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -1163,11 +1163,6 @@ void gr_gm20b_init_cyclestats(struct gk20a *g)
#endif
}
void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem)
{
g->ops.gr.ctxsw_prog.set_cde_enabled(g, mem);
}
void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
{
/* Check if we have at least one valid warp */

1
drivers/gpu/nvgpu/gm20b/gr_gm20b.h
View File

@@ -109,7 +109,6 @@ u32 gr_gm20b_get_max_lts_per_ltc(struct gk20a *g);
u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g);
u32 gr_gm20b_get_max_fbps_count(struct gk20a *g);
void gr_gm20b_init_cyclestats(struct gk20a *g);
void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem);
void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);
void gr_gm20b_get_access_map(struct gk20a *g,
u32 **whitelist, int *num_entries);

1
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -268,7 +268,6 @@ static const struct gpu_ops gm20b_ops = {
.wait_empty = gr_gk20a_wait_idle,
.init_cyclestats = gr_gm20b_init_cyclestats,
.set_sm_debug_mode = gr_gk20a_set_sm_debug_mode,
.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
.bpt_reg_info = gr_gm20b_bpt_reg_info,
.get_access_map = gr_gm20b_get_access_map,
.handle_fecs_error = gk20a_gr_handle_fecs_error,

13
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -2156,8 +2156,10 @@ int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
goto enable_ch;
}
if (g->ops.gr.update_boosted_ctx != NULL) {
g->ops.gr.update_boosted_ctx(g, mem, gr_ctx);
if (g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies !=
NULL) {
g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies(g,
mem, gr_ctx->boosted_ctx);
} else {
err = -ENOSYS;
}
@@ -2168,13 +2170,6 @@ enable_ch:
return err;
}
void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct nvgpu_mem *mem,
struct nvgpu_gr_ctx *gr_ctx)
{
g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies(g, mem,
gr_ctx->boosted_ctx);
}
int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
u32 graphics_preempt_mode,
u32 compute_preempt_mode)

2
drivers/gpu/nvgpu/gp10b/gr_gp10b.h
View File

@@ -134,8 +134,6 @@ int gr_gp10b_suspend_contexts(struct gk20a *g,
int *ctx_resident_ch_fd);
int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch,
bool boost);
void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct nvgpu_mem *mem,
struct nvgpu_gr_ctx *gr_ctx);
int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
u32 graphics_preempt_mode,
u32 compute_preempt_mode);

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -291,7 +291,6 @@ static const struct gpu_ops gp10b_ops = {
.wait_empty = gr_gp10b_wait_empty,
.init_cyclestats = gr_gm20b_init_cyclestats,
.set_sm_debug_mode = gr_gk20a_set_sm_debug_mode,
.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
.bpt_reg_info = gr_gm20b_bpt_reg_info,
.get_access_map = gr_gp10b_get_access_map,
.handle_fecs_error = gr_gp10b_handle_fecs_error,
@@ -343,7 +342,6 @@ static const struct gpu_ops gp10b_ops = {
.pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
.init_preemption_state = gr_gp10b_init_preemption_state,
.update_boosted_ctx = gr_gp10b_update_boosted_ctx,
.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,
.init_ecc = gp10b_ecc_init,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -396,7 +396,6 @@ static const struct gpu_ops gv100_ops = {
.wait_empty = gr_gv11b_wait_empty,
.init_cyclestats = gr_gm20b_init_cyclestats,
.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode,
.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
.bpt_reg_info = gv11b_gr_bpt_reg_info,
.get_access_map = gr_gv11b_get_access_map,
.handle_fecs_error = gr_gv11b_handle_fecs_error,
@@ -450,7 +449,6 @@ static const struct gpu_ops gv100_ops = {
.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.init_preemption_state = NULL,
.update_boosted_ctx = gr_gp10b_update_boosted_ctx,
.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
.set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,

4
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -344,7 +344,6 @@ static const struct gpu_ops gv11b_ops = {
.wait_empty = gr_gv11b_wait_empty,
.init_cyclestats = gr_gm20b_init_cyclestats,
.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode,
.enable_cde_in_fecs = NULL,
.bpt_reg_info = gv11b_gr_bpt_reg_info,
.get_access_map = gr_gv11b_get_access_map,
.handle_fecs_error = gr_gv11b_handle_fecs_error,
@@ -398,7 +397,6 @@ static const struct gpu_ops gv11b_ops = {
.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.init_preemption_state = gr_gv11b_init_preemption_state,
.update_boosted_ctx = gr_gp10b_update_boosted_ctx,
.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
.set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
.init_ecc = gv11b_ecc_init,
@@ -496,7 +494,7 @@ static const struct gpu_ops gv11b_ops = {
gp10b_ctxsw_prog_set_compute_preemption_mode_cilp,
.set_graphics_preemption_mode_gfxp =
gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp,
.set_cde_enabled = gm20b_ctxsw_prog_set_cde_enabled,
.set_cde_enabled = NULL,
.set_pc_sampling = gm20b_ctxsw_prog_set_pc_sampling,
.set_priv_access_map_config_mode =
gm20b_ctxsw_prog_set_priv_access_map_config_mode,

5
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -365,8 +365,6 @@ struct gpu_ops {
int (*wait_empty)(struct gk20a *g, unsigned long duration_ms,
u32 expect_delay);
void (*init_cyclestats)(struct gk20a *g);
void (*enable_cde_in_fecs)(struct gk20a *g,
struct nvgpu_mem *mem);
int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch,
u64 sms, bool enable);
void (*bpt_reg_info)(struct gk20a *g,
@@ -438,9 +436,6 @@ struct gpu_ops {
u32 graphics_preempt_mode,
u32 compute_preempt_mode);
int (*set_boosted_ctx)(struct channel_gk20a *ch, bool boost);
void (*update_boosted_ctx)(struct gk20a *g,
struct nvgpu_mem *mem,
struct nvgpu_gr_ctx *gr_ctx);
int (*init_sm_id_table)(struct gk20a *g);
int (*load_smid_config)(struct gk20a *g);
void (*program_sm_id_numbering)(struct gk20a *g,

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -412,7 +412,6 @@ static const struct gpu_ops tu104_ops = {
.wait_empty = gr_gv11b_wait_empty,
.init_cyclestats = gr_gm20b_init_cyclestats,
.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode,
.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
.bpt_reg_info = gv11b_gr_bpt_reg_info,
.get_access_map = gr_gv11b_get_access_map,
.handle_fecs_error = gr_gv11b_handle_fecs_error,
@@ -466,7 +465,6 @@ static const struct gpu_ops tu104_ops = {
.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.init_preemption_state = gr_gv11b_init_preemption_state,
.update_boosted_ctx = gr_gp10b_update_boosted_ctx,
.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
.set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
.init_ecc = tu104_ecc_init,

5
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -155,7 +155,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.wait_empty = NULL,
.init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
.bpt_reg_info = NULL,
.get_access_map = gr_gp10b_get_access_map,
.handle_fecs_error = NULL,
@@ -207,7 +206,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.pre_process_sm_exception = NULL,
.set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
.init_preemption_state = NULL,
.update_boosted_ctx = NULL,
.set_bes_crop_debug3 = NULL,
.set_bes_crop_debug4 = NULL,
.set_ctxsw_preemption_mode =
@@ -298,8 +296,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
.set_pmu_options_boost_clock_frequencies =
gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies,
.set_pmu_options_boost_clock_frequencies = NULL,
.set_full_preemption_ptr =
gp10b_ctxsw_prog_set_full_preemption_ptr,
.dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats,

5
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -170,7 +170,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.wait_empty = NULL,
.init_cyclestats = vgpu_gr_gm20b_init_cyclestats,
.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
.bpt_reg_info = NULL,
.get_access_map = gr_gv11b_get_access_map,
.handle_fecs_error = NULL,
@@ -221,7 +220,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.pre_process_sm_exception = NULL,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.init_preemption_state = NULL,
.update_boosted_ctx = NULL,
.set_bes_crop_debug3 = NULL,
.set_bes_crop_debug4 = NULL,
.set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode,
@@ -337,8 +335,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
gm20b_ctxsw_prog_get_ts_buffer_aperture_mask,
.set_ts_num_records = gm20b_ctxsw_prog_set_ts_num_records,
.set_ts_buffer_ptr = gm20b_ctxsw_prog_set_ts_buffer_ptr,
.set_pmu_options_boost_clock_frequencies =
gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies,
.set_pmu_options_boost_clock_frequencies = NULL,
.set_full_preemption_ptr =
gv11b_ctxsw_prog_set_full_preemption_ptr,
.set_full_preemption_ptr_veid0 =