diff --git a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
index 917498aaa..48d614aaf 100644
--- a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
@@ -292,7 +292,7 @@ void ga10b_gsp_enable_irq(struct gk20a *g, bool enable)
 	}
 }
 
-static int gsp_get_emem_boundaries(struct gk20a *g,
+s32 ga10b_gsp_get_emem_boundaries(struct gk20a *g,
 	u32 *start_emem, u32 *end_emem)
 {
 	u32 tag_width_shift = 0;
@@ -357,7 +357,7 @@ static int gsp_memcpy_params_check(struct gk20a *g, u32 dmem_addr,
 		goto exit;
 	}
 
-	status = gsp_get_emem_boundaries(g, &start_emem, &end_emem);
+	status = ga10b_gsp_get_emem_boundaries(g, &start_emem, &end_emem);
 	if (status != 0) {
 		goto exit;
 	}
@@ -402,7 +402,7 @@ static int ga10b_gsp_emem_transfer(struct gk20a *g, u32 dmem_addr, u8 *buf,
 	emem_d_offset = pgsp_ememd_r(port);
 
 	/* Only start address needed */
-	status = gsp_get_emem_boundaries(g, &start_emem, NULL);
+	status = ga10b_gsp_get_emem_boundaries(g, &start_emem, NULL);
 	if (status != 0) {
 		goto exit;
 	}
diff --git a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h
index 311babfff..5396e9708 100644
--- a/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.h
@@ -48,6 +48,8 @@ int ga10b_gsp_flcn_copy_from_emem(struct gk20a *g,
 
 /* interrupt */
 void ga10b_gsp_enable_irq(struct gk20a *g, bool enable);
+s32 ga10b_gsp_get_emem_boundaries(struct gk20a *g,
+	u32 *start_emem, u32 *end_emem);
 void ga10b_gsp_isr(struct gk20a *g, struct nvgpu_gsp *gsp);
 void ga10b_gsp_set_msg_intr(struct gk20a *g);
 #endif /* CONFIG_NVGPU_GSP_SCHEDULER */
diff --git a/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.h b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.h
index eda8f56c7..3922f6066 100644
--- a/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.h
+++ b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -40,5 +40,10 @@ void gv11b_mm_mmu_fault_handle_other_fault_notify(struct gk20a *g,
 						  u32 fault_status);
 
 void gv11b_mm_mmu_fault_parse_mmu_fault_info(struct mmu_fault_info *mmufault);
+void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
+	 struct nvgpu_mem *mem, u32 offset, struct mmu_fault_info *mmufault);
+bool gv11b_mm_mmu_fault_handle_mmu_fault_refch(struct gk20a *g,
+		struct mmu_fault_info *mmufault, u32 *id_ptr,
+		unsigned int *id_type_ptr, unsigned int *rc_type_ptr);
 
 #endif
diff --git a/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c
index a8b58b691..c41349910 100644
--- a/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c
@@ -198,7 +198,7 @@ void gv11b_mm_mmu_fault_parse_mmu_fault_info(struct mmu_fault_info *mmufault)
  *|V|R|P|  gpc_id |0 0 0|t|0|acctp|0|   client    |RF0 0|faulttype|
  */
 
-static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
+void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g,
 	 struct nvgpu_mem *mem, u32 offset, struct mmu_fault_info *mmufault)
 {
 	u32 rd32_val;
@@ -341,7 +341,7 @@ static bool gv11b_mm_mmu_fault_handle_mmu_fault_ce(struct gk20a *g,
 	return false;
 }
 
-static bool gv11b_mm_mmu_fault_handle_mmu_fault_refch(struct gk20a *g,
+bool gv11b_mm_mmu_fault_handle_mmu_fault_refch(struct gk20a *g,
 		struct mmu_fault_info *mmufault, u32 *id_ptr,
 		unsigned int *id_type_ptr, unsigned int *rc_type_ptr)
 {