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gpu: nvgpu: fix gpc_tpc_mask to use max_gpc_count

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gpc_tpc_mask uses gpc/tpc IDs directly read from fuse, so it needs to
use max_gpc_count for any possible cases rather not gpc_count.

Bug 2302005

Change-Id: I903ee3e0c10c4b329dd0d76c40d3516dc36ed303
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790464
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2018-08-01 11:38:17 -07:00
committed by mobile promotions
parent 9b9a549205
commit 6c9daf7626
2 changed files with 10 additions and 7 deletions
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2
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
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@@ -515,7 +515,7 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g,
{
struct gr_gk20a *gr = &g->gr;
int err = 0;
const u32 gpc_tpc_mask_size = sizeof(u32) * gr->gpc_count;
const u32 gpc_tpc_mask_size = sizeof(u32) * gr->max_gpc_count;
if (args->mask_buf_size > 0) {
size_t write_size = gpc_tpc_mask_size;