diff --git a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c
index af42fc81b..8e904099e 100644
--- a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c
+++ b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c
@@ -428,6 +428,7 @@ static int nvgpu_set_pd_level_is_next_level_pde(struct vm_gk20a *vm,
  * phys_addr will always point to a contiguous range - the discontiguous nature
  * of DMA buffers is taken care of at the layer above this.
  */
+NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 17_2), "TID-278")
 static int nvgpu_set_pd_level(struct vm_gk20a *vm,
 			      struct nvgpu_gmmu_pd *pd,
 			      u32 lvl,
@@ -543,6 +544,7 @@ static int nvgpu_set_pd_level(struct vm_gk20a *vm,
 
 	return 0;
 }
+NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 17_2))
 
 static int nvgpu_gmmu_do_update_page_table_sgl(struct vm_gk20a *vm,
 				struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl,
diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c
index 38d8159a8..95112613f 100644
--- a/drivers/gpu/nvgpu/common/mm/vm.c
+++ b/drivers/gpu/nvgpu/common/mm/vm.c
@@ -181,6 +181,7 @@ u32 nvgpu_vm_pde_coverage_bit_count(struct vm_gk20a *vm)
 	return vm->mmu_levels[final_pde_level].lo_bit[0];
 }
 
+NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 17_2), "TID-278")
 static void nvgpu_vm_do_free_entries(struct vm_gk20a *vm,
 				     struct nvgpu_gmmu_pd *pd,
 				     u32 level)
@@ -206,6 +207,7 @@ static void nvgpu_vm_do_free_entries(struct vm_gk20a *vm,
 		pd->entries = NULL;
 	}
 }
+NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 17_2))
 
 static void nvgpu_vm_free_entries(struct vm_gk20a *vm,
 				  struct nvgpu_gmmu_pd *pdb)