From 6d0ef6473d5f1bf66ea3060b9ab1d7f0ac724946 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Fri, 1 Nov 2019 10:13:21 -0400 Subject: [PATCH] gpu: nvgpu: mm: whitelist MISRA 17.2 violations Whitelist 2 MISRA Rule 17.2 violations in MM that were approved as deviations in TID-278. These two violations are for recursive functions that handle page table descriptors in the GMMU page table. Both cases are tightly controlled recursion by limiting the recursion depth to the number of possible page table levels in the hardware. For current hardware that is a maximum recursion depth of 5 which is easily an acceptable depth and should cause no stack issues. JIRA NVGPU-3489 JIRA NVGPU-3492 JIRA TID-278 Change-Id: I5b801ff77f66bb8698f1d6adcd41ebbad3f86f92 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/2230077 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/mm/gmmu/page_table.c | 2 ++ drivers/gpu/nvgpu/common/mm/vm.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c index af42fc81b..8e904099e 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu/page_table.c @@ -428,6 +428,7 @@ static int nvgpu_set_pd_level_is_next_level_pde(struct vm_gk20a *vm, * phys_addr will always point to a contiguous range - the discontiguous nature * of DMA buffers is taken care of at the layer above this. */ +NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 17_2), "TID-278") static int nvgpu_set_pd_level(struct vm_gk20a *vm, struct nvgpu_gmmu_pd *pd, u32 lvl, @@ -543,6 +544,7 @@ static int nvgpu_set_pd_level(struct vm_gk20a *vm, return 0; } +NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 17_2)) static int nvgpu_gmmu_do_update_page_table_sgl(struct vm_gk20a *vm, struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c index 38d8159a8..95112613f 100644 --- a/drivers/gpu/nvgpu/common/mm/vm.c +++ b/drivers/gpu/nvgpu/common/mm/vm.c @@ -181,6 +181,7 @@ u32 nvgpu_vm_pde_coverage_bit_count(struct vm_gk20a *vm) return vm->mmu_levels[final_pde_level].lo_bit[0]; } +NVGPU_COV_WHITELIST_BLOCK_BEGIN(deviate, 1, NVGPU_MISRA(Rule, 17_2), "TID-278") static void nvgpu_vm_do_free_entries(struct vm_gk20a *vm, struct nvgpu_gmmu_pd *pd, u32 level) @@ -206,6 +207,7 @@ static void nvgpu_vm_do_free_entries(struct vm_gk20a *vm, pd->entries = NULL; } } +NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 17_2)) static void nvgpu_vm_free_entries(struct vm_gk20a *vm, struct nvgpu_gmmu_pd *pdb)