gpu: nvgpu: move linux clk calls to tegra specific file

clk_gm20b.c has number of calls specific to linux and
tegra-soc environment
In order to unify the driver, move all of those calls
to tegra/linux specific file tegra/linux/clk.c

All the clk_*() and tegra_dvfs_*() calls are now
abstracted behind GPU's clock operations and shoule be
accessed using g->ops.clk.<API> format

Remove <linux/clk.h> and <soc/tegra/tegra-dvfs.h> from
clk_gm20b.c

Remove <linux/version.h> from clk_gm20b.c too since
we only support k4.4 and higher version only

Jira NVGPU-49

Change-Id: Ib26811e0423bbd3868b9a46e662b80a8ca088dc5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483092
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/tegra/linux/clk.c

@@ -17,6 +17,9 @@
  */
 
 #include <linux/clk.h>
+#include <linux/version.h>
+
+#include <soc/tegra/tegra-dvfs.h>
 
 #include "clk.h"
 #include "gk20a/gk20a.h"
@@ -71,8 +74,60 @@ static int nvgpu_linux_clk_set_rate(struct gk20a *g,
 	return ret;
 }
 
+static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct clk_gk20a *clk)
+{
+	/*
+	 * On Tegra GPU clock exposed to frequency governor is a shared user on
+	 * GPCPLL bus (gbus). The latter can be accessed as GPU clock parent.
+	 * Respectively the grandparent is PLL reference clock.
+	 */
+	return tegra_dvfs_get_fmax_at_vmin_safe_t(
+			clk_get_parent(clk->tegra_clk));
+}
+
+static u32 nvgpu_linux_get_ref_clock_rate(struct gk20a *g)
+{
+	struct clk *c;
+
+	c = clk_get_sys("gpu_ref", "gpu_ref");
+	if (IS_ERR(c)) {
+		nvgpu_err(g, "failed to get GPCPLL reference clock");
+		return 0;
+	}
+
+	return clk_get_rate(c);
+}
+
+static int nvgpu_linux_predict_mv_at_hz_cur_tfloor(struct clk_gk20a *clk,
+	unsigned long rate)
+{
+	return tegra_dvfs_predict_mv_at_hz_cur_tfloor(
+				clk_get_parent(clk->tegra_clk), rate);
+}
+
+static unsigned long nvgpu_linux_get_maxrate(struct clk_gk20a *clk)
+{
+	return tegra_dvfs_get_maxrate(clk_get_parent(clk->tegra_clk));
+}
+
+static int nvgpu_linux_prepare_enable(struct clk_gk20a *clk)
+{
+	return clk_prepare_enable(clk->tegra_clk);
+}
+
+static void nvgpu_linux_disable_unprepare(struct clk_gk20a *clk)
+{
+	clk_disable_unprepare(clk->tegra_clk);
+}
+
 void nvgpu_linux_init_clk_support(struct gk20a *g)
 {
 	g->ops.clk.get_rate = nvgpu_linux_clk_get_rate;
 	g->ops.clk.set_rate = nvgpu_linux_clk_set_rate;
+	g->ops.clk.get_fmax_at_vmin_safe = nvgpu_linux_get_fmax_at_vmin_safe;
+	g->ops.clk.get_ref_clock_rate = nvgpu_linux_get_ref_clock_rate;
+	g->ops.clk.predict_mv_at_hz_cur_tfloor = nvgpu_linux_predict_mv_at_hz_cur_tfloor;
+	g->ops.clk.get_maxrate = nvgpu_linux_get_maxrate;
+	g->ops.clk.prepare_enable = nvgpu_linux_prepare_enable;
+	g->ops.clk.disable_unprepare = nvgpu_linux_disable_unprepare;
 }