diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b_fusa.c index 9e7254f4f..411dcaef6 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gm20b_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -43,7 +43,12 @@ void gm20b_ramin_set_big_page_size(struct gk20a *g, if (size == SZ_64K) { val |= ram_in_big_page_size_64kb_f(); } else { +#ifndef CONFIG_NVGPU_HAL_NON_FUSA + nvgpu_err(g, "only SZ_64K is allowed"); + return; +#else val |= ram_in_big_page_size_128kb_f(); +#endif } nvgpu_mem_wr32(g, mem, ram_in_big_page_size_w(), val); diff --git a/userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.c b/userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.c index 5e9d768f2..8c94971f6 100644 --- a/userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.c +++ b/userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -22,6 +22,7 @@ #include #include +#include #include #include @@ -106,8 +107,77 @@ done: return ret; } +int test_gm20b_ramin_set_big_page_size_bvec(struct unit_module *m, struct gk20a *g, + void *args) +{ + struct nvgpu_mem mem; + int ret = UNIT_FAIL; + int err; + u32 size; + u32 data = 1U; + u32 invalid_ranges[][2] = {{0, SZ_64K - 1}, {SZ_64K + 1, U32_MAX}}; + u32 size_range_len; + + g->ops.ramin.alloc_size = gk20a_ramin_alloc_size; + + err = nvgpu_dma_alloc(g, g->ops.ramin.alloc_size(), &mem); + unit_assert(err == 0, goto done); + + /* Valid case */ + size = SZ_64K; + nvgpu_mem_wr32(g, &mem, ram_in_big_page_size_w(), data); + gm20b_ramin_set_big_page_size(g, &mem, size); + unit_assert(nvgpu_mem_rd32(g, &mem, + ram_in_big_page_size_w()) == (data | ram_in_big_page_size_64kb_f()), goto done); + unit_info(m, "BVEC testing for gm20b_ramin_set_big_page_size with size = %u(Valid Range) done\n", size); + + /* + * j is to loop through different ranges within ith case + * states is for min, max and median + */ + u32 j, states; + const char *string_states[] = {"Min", "Max", "Mid"}; + u32 size_range_difference; + + /* select appropriate size */ + size_range_len = ARRAY_SIZE(invalid_ranges); + for (j = 0; j < size_range_len; j++) { + for (states = 0; states < 3; states++) { + /* check for min size */ + if (states == 0) + size = invalid_ranges[j][0]; + else if (states == 1) { + /* check for max size */ + size = invalid_ranges[j][1]; + } else { + size_range_difference = invalid_ranges[j][1] - invalid_ranges[j][0]; + /* Check for random size in range */ + if (size_range_difference > 1) + size = get_random_u32(invalid_ranges[j][0] + 1, invalid_ranges[j][1] - 1); + else + continue; + } + + nvgpu_mem_wr32(g, &mem, ram_in_big_page_size_w(), data); + gm20b_ramin_set_big_page_size(g, &mem, size); + unit_assert(nvgpu_mem_rd32(g, &mem, ram_in_big_page_size_w()) == data, goto done); + unit_info(m, "BVEC testing for gm20b_ramin_set_big_page_size with size = 0x%08x(Invalid range [0x%08x - 0x%08x] %s)\n", size, invalid_ranges[j][0], invalid_ranges[j][1], string_states[states]); + } + } + + ret = UNIT_SUCCESS; +done: + if (ret != UNIT_SUCCESS) { + unit_err(m, "Failed Test %s", __func__); + } + + nvgpu_dma_free(g, &mem); + return ret; +} + struct unit_module_test ramin_gm20b_fusa_tests[] = { UNIT_TEST(set_big_page_size, test_gm20b_ramin_set_big_page_size, NULL, 0), + UNIT_TEST(set_big_page_size, test_gm20b_ramin_set_big_page_size_bvec, NULL, 0), }; UNIT_MODULE(ramin_gm20b_fusa, ramin_gm20b_fusa_tests, UNIT_PRIO_NVGPU_TEST); diff --git a/userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.h b/userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.h index 2777c7ff5..f97410c68 100644 --- a/userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.h +++ b/userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -52,6 +52,30 @@ struct gk20a; int test_gm20b_ramin_set_big_page_size(struct unit_module *m, struct gk20a *g, void *args); +/** + * Test specification for: test_gm20b_ramin_set_big_page_size + * + * Description: Test big page size boundary values + * + * Test Type: Boundary Value + * + * Targets: gops_ramin.set_big_page_size, gm20b_ramin_set_big_page_size + * + * Input: None + * Equivalence classes: + * size + * - Invalid : { 0 - (SZ_64K - 1), (SZ_64K + 1) - U32_MAX } + * - Valid : { SZ_64K } + * + * Steps: + * - Set big page size in given instance block. + * - Check that ramin region is updated if a valid big page size is provided. + * - Check that ramin region is not updated if an invalid big page size is provided. + * + * Output: Returns PASS if all branches gave expected results. FAIL otherwise. + */ +int test_gm20b_ramin_set_big_page_size_bvec(struct unit_module *m, struct gk20a *g, + void *args); /** * @} */ diff --git a/userspace/units/fifo/runlist/nvgpu-runlist.c b/userspace/units/fifo/runlist/nvgpu-runlist.c index 850b075f5..dee240547 100644 --- a/userspace/units/fifo/runlist/nvgpu-runlist.c +++ b/userspace/units/fifo/runlist/nvgpu-runlist.c @@ -21,6 +21,7 @@ */ #include +#include /* * Place holder for runlist unit tests. These will be written once the new diff --git a/userspace/units/fifo/runlist/nvgpu-runlist.h b/userspace/units/fifo/runlist/nvgpu-runlist.h index 399e31cda..a6f088ea8 100644 --- a/userspace/units/fifo/runlist/nvgpu-runlist.h +++ b/userspace/units/fifo/runlist/nvgpu-runlist.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -135,12 +135,16 @@ int test_runlist_interleave_level_name(struct unit_module *m, * * Description: Reload given runlists. * - * Test Type: Feature + * Test Type: Feature, Boundary Value * * Targets: gops_runlist.reload, nvgpu_runlist_reload, * nvgpu_runlist_reload_ids, nvgpu_runlist_update * * Input: test_fifo_init_support + * Equivalence classes: + * runlist id + * - Invalid : { 2 - U32_MAX } + * - Valid: { 0, 1 } * * Steps: * - Reload runlist with different conditions: @@ -149,6 +153,8 @@ int test_runlist_interleave_level_name(struct unit_module *m, * - Pending wait times out. * - Runlist update pending wait is interrupted. * - Remove/Restore all channels. + * - Verify error for runlist ids for Invalid range + * - Verify pass for runlist ids for valid range * * Output: Returns PASS if all branches gave expected results. FAIL otherwise. */ @@ -159,17 +165,23 @@ int test_runlist_reload_ids(struct unit_module *m, struct gk20a *g, void *args); * * Description: Add/remove channel from runlist. * - * Test Type: Feature + * Test Type: Feature, Boundary Value * * Targets: nvgpu_runlist_update_locked, gk20a_runlist_modify_active_locked, * gk20a_runlist_reconstruct_locked * * Input: test_fifo_init_support + * Equivalence classes: + * runlist_id + * - Invalid : { 2 - U32_MAX } + * - Valid : { 0 - 1 } * * Steps: * - Check that channels can be added to runlist. * - Check that channels can be removed from runlist. * - Check that runlist update fails for invalid tsg id and zero runlist entries + * - Check that runlist update fails for invalid runlist ids + * - Check that runlist update passes for valid runlist ids * * Output: Returns PASS if all branches gave expected results. FAIL otherwise. */