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gpu: nvgpu: rework regops execution API

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Rework regops execution API to accomodate below updates for new
profiler design

- gops.regops.exec_regops() should accept TSG pointer instead of
  channel pointer.
- Remove individual boolean parameters and add one flag field.

Below new flags are added to this API :
NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE
NVGPU_REG_OP_FLAG_MODE_CONTINUE_ON_ERROR
NVGPU_REG_OP_FLAG_ALL_PASSED
NVGPU_REG_OP_FLAG_DIRECT_OPS

Update other APIs, e.g. gr_gk20a_exec_ctx_ops() and validate_reg_ops()
as per new API changes.

Add new API gk20a_is_tsg_ctx_resident() to check context residency
from TSG pointer.

Convert gr_gk20a_ctx_patch_smpc() to a HAL gops.gr.ctx_patch_smpc().
Set this HAL only for gm20b since it is not required for later chips.
Also, remove subcontext code from this function since gm20b does not
support subcontext.

Remove stale comment about missing vGPU support in exec_regops_gk20a()

Bug 2510974
Jira NVGPU-5360

Change-Id: I3c25c34277b5ca88484da1e20d459118f15da102
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2389733
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2020-07-29 18:25:19 +05:30
committed by Alex Waterman
parent a73b5d3c6f
commit 6daa0636d1
13 changed files with 172 additions and 131 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -422,11 +422,10 @@ struct gpu_ops {
#ifdef CONFIG_NVGPU_DEBUGGER
struct {
int (*exec_regops)(struct gk20a *g,
struct nvgpu_channel *ch,
struct nvgpu_dbg_reg_op *ops,
u32 num_ops,
bool is_profiler,
bool *is_current_ctx);
struct nvgpu_tsg *tsg,
struct nvgpu_dbg_reg_op *ops,
u32 num_ops,
u32 *flags);
const struct regop_offset_range* (
*get_global_whitelist_ranges)(void);
u64 (*get_global_whitelist_ranges_count)(void);

3
drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
View File

@@ -1109,6 +1109,9 @@ struct gops_gr {
struct nvgpu_tsg *tsg,
u64 gpu_va,
u32 mode);
int (*ctx_patch_smpc)(struct gk20a *g,
u32 addr, u32 data,
struct nvgpu_gr_ctx *gr_ctx);
void (*init_hwpm_pmm_register)(struct gk20a *g);
void (*get_num_hwpm_perfmon)(struct gk20a *g, u32 *num_sys_perfmon,
u32 *num_fbp_perfmon,

15
drivers/gpu/nvgpu/include/nvgpu/regops.h
View File

@@ -26,6 +26,11 @@
#ifdef CONFIG_NVGPU_DEBUGGER
#include <nvgpu/types.h>
struct gk20a;
struct nvgpu_tsg;
/*
* Register operations
* All operations are targeted towards first channel
@@ -57,6 +62,11 @@
#define NVGPU_DBG_REG_OP_STATUS_UNSUPPORTED_OP 0x00000008U
#define NVGPU_DBG_REG_OP_STATUS_INVALID_MASK 0x00000010U
#define NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE BIT32(1U)
#define NVGPU_REG_OP_FLAG_MODE_CONTINUE_ON_ERROR BIT32(2U)
#define NVGPU_REG_OP_FLAG_ALL_PASSED BIT32(3U)
#define NVGPU_REG_OP_FLAG_DIRECT_OPS BIT32(4U)
struct nvgpu_dbg_reg_op {
u8 op;
u8 type;
@@ -77,11 +87,10 @@ struct regop_offset_range {
};
int exec_regops_gk20a(struct gk20a *g,
struct nvgpu_channel *ch,
struct nvgpu_tsg *tsg,
struct nvgpu_dbg_reg_op *ops,
u32 num_ops,
bool is_profiler,
bool *is_current_ctx);
u32 *flags);
/* turn seriously unwieldy names -> something shorter */
#define REGOP(x) NVGPU_DBG_REG_OP_##x

5
drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
View File

@@ -328,10 +328,9 @@ struct tegra_vgpu_reg_op {
};
struct tegra_vgpu_reg_ops_params {
u64 handle;
u64 num_ops;
u32 is_profiler;
u8 is_current_ctx;
u32 tsg_id;
u32 flags;
};
struct tegra_vgpu_channel_priority_params {