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gpu: nvgpu: Move is_fmodel to struct gk20a

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Copy is_fmodel to struct gk20a at probe time, and access it from
gk20a instead of platform_gk20a.

JIRA NVGPU-16

Change-Id: Ib8d793ea2b02b62da3bfdbb6372d9927658b7ec6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463540
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Terje Bergstrom
2017-04-14 13:11:18 -07:00
committed by mobile promotions
parent 15e9b433f3
commit 6df49a63ca
17 changed files with 34 additions and 56 deletions
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7
drivers/gpu/nvgpu/common/linux/module.c
View File

@@ -212,11 +212,6 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
if (g->irq_stall != g->irq_nonstall)
disable_irq(g->irq_nonstall);
/*
* is_fmodel needs to be in gk20a struct for deferred teardown
*/
g->is_fmodel = platform->is_fmodel;
/* Decrement platform power refcount */
if (platform->idle)
platform->idle(dev);
@@ -885,7 +880,7 @@ static int gk20a_probe(struct platform_device *dev)
gk20a->dev = &dev->dev;
if (nvgpu_platform_is_simulation(gk20a))
platform->is_fmodel = true;
gk20a->is_fmodel = true;
nvgpu_kmem_init(gk20a);

5
drivers/gpu/nvgpu/common/linux/pci.c
View File

@@ -402,11 +402,6 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
}
disable_irq(g->irq_stall);
/*
* is_fmodel needs to be in gk20a struct for deferred teardown
*/
g->is_fmodel = platform->is_fmodel;
err = nvgpu_pci_init_support(pdev);
if (err)
return err;

4
drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
View File

@@ -442,9 +442,7 @@ done:
int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr)
{
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
if (platform->is_fmodel)
if (g->is_fmodel)
return gr_gk20a_init_ctx_vars_sim(g, gr);
else
return gr_gk20a_init_ctx_vars_fw(g, gr);

11
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -380,10 +380,9 @@ int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms,
{
u32 val;
u32 delay = expect_delay;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
struct nvgpu_timeout timeout;
if (platform->is_fmodel)
if (g->is_fmodel)
return 0;
gk20a_dbg_fn("");
@@ -1581,7 +1580,6 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load;
struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init;
u32 last_method_data = 0;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header;
struct nvgpu_mem *ctxheader = &ctx->mem;
@@ -1595,7 +1593,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
if (gr->ctx_vars.golden_image_initialized) {
goto clean_up;
}
if (!platform->is_fmodel) {
if (!g->is_fmodel) {
struct nvgpu_timeout timeout;
nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000,
@@ -1638,7 +1636,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r());
nvgpu_udelay(10);
if (!platform->is_fmodel) {
if (!g->is_fmodel) {
struct nvgpu_timeout timeout;
nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000,
@@ -2580,11 +2578,10 @@ static void gr_gk20a_load_falcon_with_bootloader(struct gk20a *g)
int gr_gk20a_load_ctxsw_ucode(struct gk20a *g)
{
int err;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
gk20a_dbg_fn("");
if (platform->is_fmodel) {
if (g->is_fmodel) {
gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7),
gr_fecs_ctxsw_mailbox_value_f(0xc0de7777));
gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7),

3
drivers/gpu/nvgpu/gk20a/ltc_common.c
View File

@@ -91,9 +91,8 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
u64 compbit_base_post_multiply64;
u64 compbit_store_iova;
u64 compbit_base_post_divide64;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
if (platform->is_fmodel)
if (g->is_fmodel)
compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem);
else
compbit_store_iova = g->ops.mm.get_iova_addr(g,

3
drivers/gpu/nvgpu/gk20a/ltc_gk20a.c
View File

@@ -49,7 +49,6 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
u32 compbit_backing_size;
int err;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
gk20a_dbg_fn("");
@@ -83,7 +82,7 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
gk20a_dbg_info("max comptag lines : %d",
max_comptag_lines);
if (platform->is_fmodel)
if (g->is_fmodel)
err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size);
else
err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size);

3
drivers/gpu/nvgpu/gk20a/platform_gk20a.h
View File

@@ -38,9 +38,6 @@ struct gk20a_platform {
/* Populated by the gk20a driver before probing the platform. */
struct gk20a *g;
/* Should be populated at probe. */
bool is_fmodel;
/* Should be populated at probe. */
bool can_railgate;

7
drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
View File

@@ -28,9 +28,7 @@
void gk20a_enable_priv_ring(struct gk20a *g)
{
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
if (platform->is_fmodel)
if (g->is_fmodel)
return;
if (g->ops.clock_gating.slcg_priring_load_gating_prod)
@@ -75,9 +73,8 @@ void gk20a_priv_ring_isr(struct gk20a *g)
s32 retry = 100;
u32 gpc;
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
if (platform->is_fmodel)
if (g->is_fmodel)
return;
status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());

3
drivers/gpu/nvgpu/gk20a/therm_gk20a.c
View File

@@ -117,7 +117,6 @@ int gk20a_elcg_init_idle_filters(struct gk20a *g)
u32 engine_id;
u32 active_engine_id = 0;
struct fifo_gk20a *f = &g->fifo;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
gk20a_dbg_fn("");
@@ -125,7 +124,7 @@ int gk20a_elcg_init_idle_filters(struct gk20a *g)
active_engine_id = f->active_engines_list[engine_id];
gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
if (platform->is_fmodel) {
if (g->is_fmodel) {
gate_ctrl = set_field(gate_ctrl,
therm_gate_ctrl_eng_delay_after_m(),
therm_gate_ctrl_eng_delay_after_f(4));

3
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -725,11 +725,10 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() -
gr_fecs_falcon_hwcfg_r();
u8 falcon_id_mask = 0;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
gk20a_dbg_fn("");
if (platform->is_fmodel) {
if (g->is_fmodel) {
gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7),
gr_fecs_ctxsw_mailbox_value_f(0xc0de7777));
gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7),

5
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -183,14 +183,13 @@ int gm20b_init_hal(struct gk20a *g)
{
struct gpu_ops *gops = &g->ops;
struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
u32 val;
gops->clock_gating = gm20b_ops.clock_gating;
gops->securegpccs = false;
gops->pmupstate = false;
#ifdef CONFIG_TEGRA_ACR
if (platform->is_fmodel) {
if (g->is_fmodel) {
gops->privsecurity = 1;
} else {
val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
@@ -202,7 +201,7 @@ int gm20b_init_hal(struct gk20a *g)
}
}
#else
if (platform->is_fmodel) {
if (g->is_fmodel) {
gk20a_dbg_info("running ASIM with PRIV security disabled");
gops->privsecurity = 0;
} else {

3
drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
View File

@@ -49,7 +49,6 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
u32 compbit_backing_size;
int err;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
gk20a_dbg_fn("");
@@ -82,7 +81,7 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
gk20a_dbg_info("max comptag lines : %d",
max_comptag_lines);
if (platform->is_fmodel)
if (g->is_fmodel)
err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size);
else
err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size);

5
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -189,13 +189,12 @@ int gp10b_init_hal(struct gk20a *g)
{
struct gpu_ops *gops = &g->ops;
struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
u32 val;
gops->clock_gating = gp10b_ops.clock_gating;
gops->pmupstate = false;
#ifdef CONFIG_TEGRA_ACR
if (platform->is_fmodel) {
if (g->is_fmodel) {
gops->privsecurity = 0;
gops->securegpccs = 0;
} else if (gk20a_gpu_is_virtual(g->dev)) {
@@ -213,7 +212,7 @@ int gp10b_init_hal(struct gk20a *g)
}
}
#else
if (platform->is_fmodel) {
if (g->is_fmodel) {
gk20a_dbg_info("running simulator with PRIV security disabled");
gops->privsecurity = 0;
gops->securegpccs = 0;

3
drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
View File

@@ -71,7 +71,6 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
u32 compbit_backing_size;
int err;
struct gk20a_platform *platform = dev_get_drvdata(g->dev);
gk20a_dbg_fn("");
@@ -102,7 +101,7 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
gk20a_dbg_info("gobs_per_comptagline_per_slice: %d",
gobs_per_comptagline_per_slice);
if (platform->is_fmodel)
if (g->is_fmodel)
err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size);
else
err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size);

17
drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c
View File

@@ -112,12 +112,13 @@ static void gk20a_tegra_secure_page_destroy(struct device *dev,
int gk20a_tegra_secure_page_alloc(struct device *dev)
{
struct gk20a_platform *platform = dev_get_drvdata(dev);
struct gk20a *g = get_gk20a(dev);
struct secure_page_buffer *secure_buffer = &platform->secure_buffer;
DEFINE_DMA_ATTRS(attrs);
dma_addr_t iova;
size_t size = PAGE_SIZE;
if (platform->is_fmodel)
if (g->is_fmodel)
return -EINVAL;
(void)dma_alloc_attrs(&tegra_vpr_dev, size, &iova,
@@ -389,10 +390,11 @@ done:
static int gk20a_tegra_railgate(struct device *dev)
{
struct gk20a *g = get_gk20a(dev);
struct gk20a_platform *platform = dev_get_drvdata(dev);
int ret = 0;
if (platform->is_fmodel ||
if (g->is_fmodel ||
!tegra_dvfs_is_rail_up(platform->gpu_rail))
return 0;
@@ -442,11 +444,12 @@ err_power_off:
static int gk20a_tegra_unrailgate(struct device *dev)
{
struct gk20a *g = get_gk20a(dev);
struct gk20a_platform *platform = dev_get_drvdata(dev);
int ret = 0;
bool first = false;
if (platform->is_fmodel)
if (g->is_fmodel)
return 0;
if (!platform->gpu_rail) {
@@ -517,10 +520,11 @@ err_clk_on:
static bool gk20a_tegra_is_railgated(struct device *dev)
{
struct gk20a *g = get_gk20a(dev);
struct gk20a_platform *platform = dev_get_drvdata(dev);
bool ret = false;
if (!platform->is_fmodel)
if (!g->is_fmodel)
ret = !tegra_dvfs_is_rail_up(platform->gpu_rail);
return ret;
@@ -534,10 +538,11 @@ static bool gk20a_tegra_is_railgated(struct device *dev)
static int gm20b_tegra_railgate(struct device *dev)
{
struct gk20a *g = get_gk20a(dev);
struct gk20a_platform *platform = dev_get_drvdata(dev);
int ret = 0;
if (platform->is_fmodel ||
if (g->is_fmodel ||
!tegra_dvfs_is_rail_up(platform->gpu_rail))
return 0;
@@ -601,7 +606,7 @@ static int gm20b_tegra_unrailgate(struct device *dev)
int ret = 0;
bool first = false;
if (platform->is_fmodel)
if (g->is_fmodel)
return 0;
#ifdef CONFIG_TEGRA_CLK_FRAMEWORK

3
drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c
View File

@@ -72,10 +72,11 @@ static void gr_gp10b_remove_sysfs(struct device *dev);
int gp10b_tegra_get_clocks(struct device *dev)
{
struct gk20a *g = get_gk20a(dev);
struct gk20a_platform *platform = dev_get_drvdata(dev);
unsigned int i;
if (platform->is_fmodel)
if (g->is_fmodel)
return 0;
platform->num_clks = 0;

5
drivers/gpu/nvgpu/vgpu/vgpu.c
View File

@@ -18,6 +18,7 @@
#include <linux/dma-mapping.h>
#include <linux/pm_runtime.h>
#include <linux/pm_qos.h>
#include <soc/tegra/chip-id.h>
#include <nvgpu/kmem.h>
#include <nvgpu/bug.h>
@@ -574,8 +575,8 @@ int vgpu_probe(struct platform_device *pdev)
}
gk20a->dev = dev;
gk20a->is_fmodel = platform->is_fmodel;
if (tegra_platform_is_linsim() || tegra_platform_is_vdk())
gk20a->is_fmodel = true;
nvgpu_kmem_init(gk20a);