From 6dfacee682a29c65b1297b1b1ce2d22851a0d463 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Mon, 27 Feb 2023 16:13:20 +0530 Subject: [PATCH] gpu: nvgpu: rd coalesce WAR applies pre-Volta WAR to disable to rd coalescing for lg, su and tex units is applicable only before Volta (i.e. Maxwell and Pascal). Hence set the hal to NULL for gv100 and gv11b. Bug 3881919 Change-Id: Iab5dd8caf6539f0bb3cc4987f2b5f114db4c2c20 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864093 Reviewed-by: Ramalingam C Reviewed-by: Ankur Kishore GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 ++-- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index a763757e8..c46fe5acc 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -1,7 +1,7 @@ /* * GV100 Tegra HAL interface * - * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -441,7 +441,7 @@ static const struct gpu_ops gv100_ops = { .clear_sm_hww = gv11b_gr_clear_sm_hww, .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, - .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .disable_rd_coalesce = NULL, .set_boosted_ctx = gr_gp10b_set_boosted_ctx, .set_preemption_mode = gr_gp10b_set_preemption_mode, .set_czf_bypass = NULL, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index db5597243..519fdb153 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B Tegra HAL interface * - * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -393,7 +393,7 @@ static const struct gpu_ops gv11b_ops = { .clear_sm_hww = gv11b_gr_clear_sm_hww, .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, - .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .disable_rd_coalesce = NULL, .set_boosted_ctx = gr_gp10b_set_boosted_ctx, .set_preemption_mode = gr_gp10b_set_preemption_mode, .set_czf_bypass = NULL,