gpu: nvgpu: add ctrl device instance ID

In order to share the TSG across different devices securely, device
instance IDs are to be exchanged for endpoint identification. Add
device instance ID field to gk20a_ctrl_priv which is generated
from gk20a level device instance id value.

Share this ID to userspace via gpu characteristics.

Bug 3677982
JIRA NVGPU-8681

Change-Id: I79d92a81c02272c52e24f5b12c452c8993137037
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2792079
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Sagar Kamble
2022-09-26 17:46:58 +05:30
committed by mobile promotions
parent 41c874a2d9
commit 6e2b592ab9
8 changed files with 60 additions and 3 deletions

View File

@@ -85,6 +85,9 @@ struct gk20a_ctrl_priv {
struct gk20a *g;
struct nvgpu_clk_session *clk_session;
struct nvgpu_cdev *cdev;
#ifdef CONFIG_NVGPU_TSG_SHARING
u64 device_instance_id;
#endif
struct nvgpu_list_node list;
struct {
@@ -146,6 +149,18 @@ int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp)
*/
priv->g = g;
#ifdef CONFIG_NVGPU_TSG_SHARING
nvgpu_mutex_acquire(&g->ctrl_dev_id_lock);
nvgpu_assert(g->ctrl_device_instance_id < U64_MAX);
g->ctrl_device_instance_id += 1ULL;
priv->device_instance_id = g->ctrl_device_instance_id;
nvgpu_mutex_release(&g->ctrl_dev_id_lock);
nvgpu_log_info(g, "opened ctrl device: %llx", priv->device_instance_id);
#endif
if (!g->sw_ready) {
err = gk20a_busy(g);
if (err)
@@ -361,7 +376,7 @@ static void nvgpu_set_preemption_mode_flags(struct gk20a *g,
static long gk20a_ctrl_ioctl_gpu_characteristics(
struct gk20a *g, u32 gpu_instance_id, struct nvgpu_gr_config *gr_config,
struct nvgpu_gpu_get_characteristics *request)
struct gk20a_ctrl_priv *priv, struct nvgpu_gpu_get_characteristics *request)
{
struct nvgpu_gpu_characteristics gpu;
long err = 0;
@@ -377,6 +392,10 @@ static long gk20a_ctrl_ioctl_gpu_characteristics(
(void) memset(&gpu, 0, sizeof(gpu));
gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
#ifdef CONFIG_NVGPU_TSG_SHARING
gpu.device_instance_id = priv->device_instance_id;
#endif
gpu.L2_cache_size = g->ops.ltc.determine_L2_size_bytes(g);
gpu.on_board_video_memory_size = 0; /* integrated GPU */
@@ -2416,7 +2435,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
#endif /* CONFIG_NVGPU_GRAPHICS */
case NVGPU_GPU_IOCTL_GET_CHARACTERISTICS:
err = gk20a_ctrl_ioctl_gpu_characteristics(g, gpu_instance_id, gr_config,
(struct nvgpu_gpu_get_characteristics *)buf);
priv, (struct nvgpu_gpu_get_characteristics *)buf);
break;
case NVGPU_GPU_IOCTL_PREPARE_COMPRESSIBLE_READ:
err = gk20a_ctrl_prepare_compressible_read(g,