diff --git a/drivers/gpu/nvgpu/common/gr/obj_ctx.c b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
index 094761ad7..312e8830f 100644
--- a/drivers/gpu/nvgpu/common/gr/obj_ctx.c
+++ b/drivers/gpu/nvgpu/common/gr/obj_ctx.c
@@ -901,6 +901,10 @@ int nvgpu_gr_obj_ctx_alloc(struct gk20a *g,
 	    g->ops.gr.init.set_default_compute_regs != NULL) {
 		g->ops.gr.init.set_default_compute_regs(g, gr_ctx);
 	}
+
+	if (g->ops.ltc.set_default_l2_max_ways_evict_last != NULL) {
+		g->ops.ltc.set_default_l2_max_ways_evict_last(g, gr_ctx);
+	}
 #endif
 
 	/*
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index 00d57dec0..e713fea19 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -376,6 +376,9 @@ static const struct gops_ltc ga10b_ops_ltc = {
 	.get_l2_max_ways_evict_last = ga10b_get_l2_max_ways_evict_last,
 	.set_l2_sector_promotion = tu104_set_l2_sector_promotion,
 #endif /* CONFIG_NVGPU_DEBUGGER */
+#ifndef CONFIG_NVGPU_NON_FUSA
+	.set_default_l2_max_ways_evict_last = ga10b_set_default_l2_max_ways_evict_last,
+#endif /*not defined CONFIG_NVGPU_NON_FUSA*/
 };
 
 #ifdef CONFIG_NVGPU_COMPRESSION
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
index 3612d1813..982888ef6 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
@@ -26,6 +26,7 @@
 #include <nvgpu/types.h>
 
 struct gk20a;
+struct nvgpu_gr_ctx;
 
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 u32 ga10b_ltc_zbc_table_size(struct gk20a *g);
@@ -41,7 +42,10 @@ void ga10b_ltc_init_fs_state(struct gk20a *g);
 int ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g);
 u64 ga10b_determine_L2_size_bytes(struct gk20a *g);
 int ga10b_lts_ecc_init(struct gk20a *g);
-
+#ifndef CONFIG_NVGPU_NON_FUSA
+void ga10b_set_default_l2_max_ways_evict_last(struct gk20a *g,
+			struct nvgpu_gr_ctx *gr_ctx);
+#endif
 #ifdef CONFIG_NVGPU_DEBUGGER
 u32 ga10b_ltc_pri_shared_addr(struct gk20a *g, u32 addr);
 int ga10b_set_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
diff --git a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
index 444cca105..80d7c676a 100644
--- a/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
@@ -27,6 +27,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/regops.h>
 #include <nvgpu/errata.h>
+#include <nvgpu/gr/ctx.h>
 
 #include "hal/gr/gr/gr_gk20a.h"
 #include "ltc_gv11b.h"
@@ -93,6 +94,25 @@ int ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g)
 	return 0;
 }
 
+#ifndef CONFIG_NVGPU_NON_FUSA
+void ga10b_set_default_l2_max_ways_evict_last(struct gk20a *g,
+		struct nvgpu_gr_ctx *gr_ctx)
+{
+	u32 reg_val;
+	nvgpu_gr_ctx_patch_write_begin(g, gr_ctx, true);
+
+	reg_val = nvgpu_readl(g, ltc_ltcs_ltss_tstg_set_mgmt0_r());
+	reg_val = set_field(reg_val,
+			ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_m(),
+			ltc_ltcs_ltss_tstg_set_mgmt0_max_evict_last_f(16));
+	nvgpu_gr_ctx_patch_write(g, gr_ctx, ltc_ltcs_ltss_tstg_set_mgmt0_r(),
+			reg_val, true);
+
+	nvgpu_gr_ctx_patch_write_end(g, gr_ctx, true);
+}
+
+#endif
+
 #ifdef CONFIG_NVGPU_DEBUGGER
 int ga10b_set_l2_max_ways_evict_last(struct gk20a *g, struct nvgpu_tsg *tsg,
 		u32 num_ways)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
index 14345179e..dccf9c4b9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
@@ -30,7 +30,7 @@
  * common.ltc interface.
  */
 struct gk20a;
-
+struct nvgpu_gr_ctx;
 /**
  * common.ltc intr subunit hal operations.
  *
@@ -412,6 +412,10 @@ struct gops_ltc {
 	int (*ecc_init)(struct gk20a *g);
 
 	void (*init_fs_state)(struct gk20a *g);
+#ifndef CONFIG_NVGPU_NON_FUSA
+	void (*set_default_l2_max_ways_evict_last)(struct gk20a *g,
+			struct nvgpu_gr_ctx *gr_ctx);
+#endif
 #if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
 	void (*set_enabled)(struct gk20a *g, bool enabled);
 #endif