From 6e67eec8d5c266f374512444f5b4569187090d4f Mon Sep 17 00:00:00 2001 From: rmylavarapu Date: Tue, 23 Apr 2019 11:43:49 +0530 Subject: [PATCH] gpu:nvgpu: Restructure P-state unit Description: Present p-state unit handle both pstate boardobj and initializing all the units. As part of restructuring, the pstate unit is separated into two units: 1) Perf_pstate: This unit will handle pstate boardobjs. 2) Pmu_pstate: This unit will initialize all the units which supoort performance states. Changes: 1) Created pmu_pstate unit. 2) Pstate boardobjs are moved under perf_pstate which is under perf unit. NVGPU-1958 Change-Id: I2c428adfe6de4992c9eeda0d4356d30290f6e8a4 Signed-off-by: rmylavarapu Reviewed-on: https://git-master.nvidia.com/r/2096339 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 3 +- drivers/gpu/nvgpu/Makefile.sources | 3 +- drivers/gpu/nvgpu/common/clk_arb/clk_arb.c | 4 +- .../gpu/nvgpu/common/clk_arb/clk_arb_gv100.c | 4 +- drivers/gpu/nvgpu/common/init/nvgpu_init.c | 6 +- drivers/gpu/nvgpu/common/pmu/clk/clk.c | 2 +- drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c | 14 +- drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c | 8 +- drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c | 2 +- .../gpu/nvgpu/common/pmu/perf/change_seq.c | 9 +- .../gpu/nvgpu/common/pmu/perf/perf_gv100.c | 2 + .../{pstate/pstate.c => perf/perf_pstate.c} | 364 +------------ .../{pstate/pstate.h => perf/perf_pstate.h} | 9 +- drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c | 1 + drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 2 +- drivers/gpu/nvgpu/common/pmu/pmu_pstate.c | 501 ++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/clk_arb.h | 4 +- drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h | 2 +- .../nvgpu/pmu/{pstate.h => perf_pstate.h} | 22 +- .../gpu/nvgpu/include/nvgpu/pmu/pmu_pstate.h | 35 ++ drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c | 2 +- drivers/gpu/nvgpu/os/linux/module.c | 5 +- 22 files changed, 606 insertions(+), 398 deletions(-) rename drivers/gpu/nvgpu/common/pmu/{pstate/pstate.c => perf/perf_pstate.c} (51%) rename drivers/gpu/nvgpu/common/pmu/{pstate/pstate.h => perf/perf_pstate.h} (87%) create mode 100644 drivers/gpu/nvgpu/common/pmu/pmu_pstate.c rename drivers/gpu/nvgpu/include/nvgpu/pmu/{pstate.h => perf_pstate.h} (80%) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pstate.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 79ec55359..7f4a73e4c 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -112,6 +112,7 @@ nvgpu-y += \ common/pmu/perf/perf_gv100.o \ common/pmu/perf/perf_ps35.o \ common/pmu/perf/change_seq.o \ + common/pmu/perf/perf_pstate.o \ common/pmu/pmgr/pwrdev.o \ common/pmu/pmgr/pmgr.o \ common/pmu/pmgr/pmgrpmu.o \ @@ -127,7 +128,7 @@ nvgpu-y += \ common/pmu/therm/thrmpmu.o \ common/pmu/lpwr/rppg.o \ common/pmu/lpwr/lpwr.o \ - common/pmu/pstate/pstate.o \ + common/pmu/pmu_pstate.o \ common/pmu/clk/clk_vin.o \ common/pmu/clk/clk_fll.o \ common/pmu/clk/clk_domain.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 3f20cdfb4..490e43d3d 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -194,7 +194,7 @@ srcs += common/sim/sim.c \ common/pmu/lsfm/lsfm_sw_gp10b.c \ common/pmu/lsfm/lsfm_sw_gv100.c \ common/pmu/lsfm/lsfm_sw_tu104.c \ - common/pmu/pstate/pstate.c \ + common/pmu/pmu_pstate.c \ common/pmu/volt/volt_dev.c \ common/pmu/volt/volt_pmu.c \ common/pmu/volt/volt_policy.c \ @@ -216,6 +216,7 @@ srcs += common/sim/sim.c \ common/pmu/perf/vfe_var.c \ common/pmu/perf/perf_gv100.c \ common/pmu/perf/perf_ps35.c \ + common/pmu/perf/perf_pstate.c \ common/pmu/perf/change_seq.c \ common/pmu/pmgr/pmgr.c \ common/pmu/pmgr/pmgrpmu.c \ diff --git a/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c b/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c index 74ffdc090..af9ceb06d 100644 --- a/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c +++ b/drivers/gpu/nvgpu/common/clk_arb/clk_arb.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include #include @@ -154,7 +154,7 @@ int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) (void) memset(table->gpc2clk_points, 0, table->gpc2clk_num_points*sizeof(struct nvgpu_clk_vf_point)); - p0_info = pstate_get_clk_set_info(g, + p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, CLKWHICH_GPCCLK); if (!p0_info) { status = -EINVAL; diff --git a/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c b/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c index e5a586925..ac3c1c6e0 100644 --- a/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c +++ b/drivers/gpu/nvgpu/common/clk_arb/clk_arb_gv100.c @@ -81,7 +81,7 @@ int gv100_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, return -EINVAL; } - p0_info = pstate_get_clk_set_info(g, + p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, clkwhich); if (p0_info == NULL) { return -EINVAL; @@ -126,7 +126,7 @@ int gv100_get_arbiter_clk_default(struct gk20a *g, u32 api_domain, return -EINVAL; } - p0_info = pstate_get_clk_set_info(g, + p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, clkwhich); if (p0_info == NULL) { return -EINVAL; diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c index 93e52d734..aa750d629 100644 --- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c +++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c @@ -43,10 +43,10 @@ #include #include #include -#include #include #include +#include bool is_nvgpu_gpu_state_valid(struct gk20a *g) { @@ -380,14 +380,14 @@ int gk20a_finalize_poweron(struct gk20a *g) nvgpu_mutex_release(&g->tpc_pg_lock); if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { - err = gk20a_init_pstate_support(g); + err = nvgpu_pmu_pstate_sw_setup(g); if (err != 0) { nvgpu_err(g, "failed to init pstates"); nvgpu_mutex_release(&g->tpc_pg_lock); goto done; } - err = gk20a_init_pstate_pmu_support(g); + err = nvgpu_pmu_pstate_pmu_setup(g); if (err != 0) { nvgpu_err(g, "failed to init pstates"); goto done; diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk.c b/drivers/gpu/nvgpu/common/pmu/clk/clk.c index cef76f652..7ee757268 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk.c @@ -27,12 +27,12 @@ #include #include #include -#include #include #include #include #include #include +#include void nvgpu_clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, void *param, u32 status) diff --git a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c index 515fad9e4..000fe82fa 100644 --- a/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -1455,7 +1455,7 @@ static int clk_set_boot_fll_clks_per_clk_domain(struct gk20a *g) BOARDOBJGRP_FOR_EACH(&(g->clk_pmu->clk_domainobjs->super.super), struct nvgpu_clk_domain *, pclk_domain, i) { - p0_clk_set_info = pstate_get_clk_set_info(g, + p0_clk_set_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, pclk_domain->domain); switch (pclk_domain->api_domain) { @@ -1542,7 +1542,7 @@ static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain, *gpcclk_domain = i; *gpcclk_clkmhz = vf_point->gpc_mhz; - p0_info = pstate_get_clk_set_info(g, + p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, CLKWHICH_GPCCLK); if (p0_info == NULL) { nvgpu_err(g, "failed to get GPCCLK P0 info"); @@ -1560,7 +1560,7 @@ static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain, (u32) BIT(i); break; case CTRL_CLK_DOMAIN_XBARCLK: - p0_info = pstate_get_clk_set_info(g, + p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, CLKWHICH_XBARCLK); if (p0_info == NULL) { nvgpu_err(g, "failed to get XBARCLK P0 info"); @@ -1586,7 +1586,7 @@ static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain, } break; case CTRL_CLK_DOMAIN_SYSCLK: - p0_info = pstate_get_clk_set_info(g, + p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, CLKWHICH_SYSCLK); if (p0_info == NULL) { nvgpu_err(g, "failed to get SYSCLK P0 info"); @@ -1612,7 +1612,7 @@ static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain, } break; case CTRL_CLK_DOMAIN_NVDCLK: - p0_info = pstate_get_clk_set_info(g, + p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, CLKWHICH_NVDCLK); if (p0_info == NULL) { nvgpu_err(g, "failed to get NVDCLK P0 info"); @@ -1638,7 +1638,7 @@ static void clk_set_p0_clk_per_domain(struct gk20a *g, u8 *gpcclk_domain, } break; case CTRL_CLK_DOMAIN_HOSTCLK: - p0_info = pstate_get_clk_set_info(g, + p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, CLKWHICH_HOSTCLK); if (p0_info == NULL) { nvgpu_err(g, "failed to get HOSTCLK P0 info"); diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c index 00e8d36cd..93c828e8e 100644 --- a/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c +++ b/drivers/gpu/nvgpu/common/pmu/lpwr/lpwr.c @@ -25,9 +25,9 @@ #include #include #include -#include #include #include +#include #include "gp106/bios_gp106.h" #include "lpwr.h" @@ -243,7 +243,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate) nvgpu_log_fn(g, " "); - pstate_info = pstate_get_clk_set_info(g, pstate, + pstate_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, pstate, CLKWHICH_MCLK); if (pstate_info == NULL) { return -EINVAL; @@ -325,7 +325,7 @@ bool nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num) &g->perf_pmu->lpwr.lwpr_bios_data.ms; struct nvgpu_lpwr_bios_idx_data *pidx_data = &g->perf_pmu->lpwr.lwpr_bios_data.idx; - struct pstate *pstate = pstate_find(g, pstate_num); + struct pstate *pstate = nvgpu_pmu_perf_pstate_find(g, pstate_num); u32 ms_idx; nvgpu_log_fn(g, " "); @@ -348,7 +348,7 @@ bool nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num) &g->perf_pmu->lpwr.lwpr_bios_data.gr; struct nvgpu_lpwr_bios_idx_data *pidx_data = &g->perf_pmu->lpwr.lwpr_bios_data.idx; - struct pstate *pstate = pstate_find(g, pstate_num); + struct pstate *pstate = nvgpu_pmu_perf_pstate_find(g, pstate_num); u32 idx; nvgpu_log_fn(g, " "); diff --git a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c index 906836879..81c9e1f64 100644 --- a/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c +++ b/drivers/gpu/nvgpu/common/pmu/lpwr/rppg.c @@ -22,10 +22,10 @@ #include #include -#include #include #include #include +#include #include "gp106/bios_gp106.h" diff --git a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c index 7a1c60322..5a43c6824 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/change_seq.c @@ -25,15 +25,16 @@ #include #include #include -#include +#include +#include #include #include #include #include #include +#include #include "pmu_perf.h" - #include "change_seq.h" #define SEQ_SCRIPT_CURR 0x0U @@ -133,8 +134,8 @@ static void build_change_seq_boot (struct gk20a *g) BOARDOBJGRP_FOR_EACH(&(g->clk_pmu->clk_domainobjs->super.super), struct nvgpu_clk_domain *, pdomain, i) { - p0_info = pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, - pdomain->domain); + p0_info = nvgpu_pmu_perf_pstate_get_clk_set_info(g, + CTRL_PERF_PSTATE_P0, pdomain->domain); script_last->buf.change.data.clk_list.clk_domains[i].clk_domain = pdomain->api_domain; diff --git a/drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c b/drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c index 4aef6911c..68d9a10ad 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include #include diff --git a/drivers/gpu/nvgpu/common/pmu/pstate/pstate.c b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c similarity index 51% rename from drivers/gpu/nvgpu/common/pmu/pstate/pstate.c rename to drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c index 07a328368..75b7253ae 100644 --- a/drivers/gpu/nvgpu/common/pmu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.c @@ -1,7 +1,7 @@ /* * general p state infrastructure * - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,352 +29,12 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include -#include +#include +#include +#include -#include "pstate.h" - -static int pstate_sw_setup(struct gk20a *g); - -void gk20a_deinit_pstate_support(struct gk20a *g) -{ - pmgr_pmu_free_pmupstate(g); - nvgpu_therm_pmu_free_pmupstate(g); - nvgpu_perf_pmu_free_pmupstate(g); - nvgpu_clk_domain_free_pmupstate(g); - nvgpu_clk_prog_free_pmupstate(g); - nvgpu_clk_vf_point_free_pmupstate(g); - nvgpu_clk_freq_domain_free_pmupstate(g); - nvgpu_clk_freq_controller_free_pmupstate(g); - nvgpu_clk_fll_free_pmupstate(g); - nvgpu_clk_vin_free_pmupstate(g); - nvgpu_clk_free_pmupstate(g); - - if (g->ops.clk.mclk_deinit != NULL) { - g->ops.clk.mclk_deinit(g); - } -} - -/*sw setup for pstate components*/ -int gk20a_init_pstate_support(struct gk20a *g) -{ - int err; - - nvgpu_log_fn(g, " "); - - err = nvgpu_pmu_wait_ready(g); - if (err != 0) { - nvgpu_err(g, "PMU not ready to process pstate requests"); - return err; - } - - err = nvgpu_clk_init_pmupstate(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_domain_init_pmupstate(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_prog_init_pmupstate(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_vf_point_init_pmupstate(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_freq_domain_init_pmupstate(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_freq_controller_init_pmupstate(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_vin_init_pmupstate(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_fll_init_pmupstate(g); - if (err != 0) { - return err; - } - - err = nvgpu_perf_pmu_init_pmupstate(g); - if (err != 0) { - goto err_clk_init_pmupstate; - } - - err = nvgpu_therm_pmu_init_pmupstate(g); - if (err != 0) { - goto err_perf_pmu_init_pmupstate; - } - - err = pmgr_pmu_init_pmupstate(g); - if (err != 0) { - goto err_therm_pmu_init_pmupstate; - } - - err = nvgpu_volt_rail_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - err = nvgpu_volt_dev_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - err = nvgpu_volt_policy_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - err = nvgpu_clk_vin_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - err = nvgpu_clk_fll_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - err = nvgpu_therm_domain_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - if (g->ops.pmu_perf.support_vfe) { - err = nvgpu_vfe_var_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - err = nvgpu_vfe_equ_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - } - - err = nvgpu_clk_domain_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - if (g->ops.clk.support_vf_point && - g->ops.pmu_perf.support_vfe) { - err = nvgpu_clk_vf_point_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - } - - err = nvgpu_clk_prog_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - if (g->ops.clk.support_clk_freq_domain) { - err = nvgpu_clk_freq_domain_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - } - - err = pstate_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - - if(g->ops.clk.support_pmgr_domain) { - err = pmgr_domain_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - } - - if (g->ops.clk.support_clk_freq_controller) { - err = nvgpu_clk_freq_controller_sw_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - } - - if(g->ops.clk.support_lpwr_pg) { - err = nvgpu_lpwr_pg_setup(g); - if (err != 0) { - goto err_pmgr_pmu_init_pmupstate; - } - } - - if(g->ops.pmu_perf.support_changeseq) { - err = nvgpu_perf_change_seq_sw_setup(g); - if (err != 0) { - goto err_clk_init_pmupstate; - } - } - - return 0; - -err_pmgr_pmu_init_pmupstate: - pmgr_pmu_free_pmupstate(g); -err_therm_pmu_init_pmupstate: - nvgpu_therm_pmu_free_pmupstate(g); -err_perf_pmu_init_pmupstate: - nvgpu_perf_pmu_free_pmupstate(g); -err_clk_init_pmupstate: - nvgpu_clk_free_pmupstate(g); - - return err; -} - -/*sw setup for pstate components*/ -int gk20a_init_pstate_pmu_support(struct gk20a *g) -{ - int err; - - nvgpu_log_fn(g, " "); - - if (g->ops.clk.mclk_init != NULL) { - err = g->ops.clk.mclk_init(g); - if (err != 0) { - nvgpu_err(g, "failed to set mclk"); - /* Indicate error and continue */ - } - } - - err = nvgpu_volt_rail_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_volt_dev_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_volt_policy_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_volt_send_load_cmd_to_pmu(g); - if (err != 0) { - nvgpu_err(g, - "Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.", - err); - return err; - } - - err = nvgpu_therm_domain_pmu_setup(g); - if (err != 0) { - return err; - } - - if (g->ops.pmu_perf.support_vfe) { - err = nvgpu_vfe_var_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_vfe_equ_pmu_setup(g); - if (err != 0) { - return err; - } - } - - err = nvgpu_clk_domain_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_prog_pmu_setup(g); - if (err != 0) { - return err; - } - - err = nvgpu_clk_vin_pmu_setup(g); - if (err != 0) { - return err; - } - - if (g->ops.clk.support_clk_freq_domain) { - err = nvgpu_clk_freq_domain_pmu_setup(g); - if (err != 0) { - return err; - } - } - - err = nvgpu_clk_fll_pmu_setup(g); - if (err != 0) { - return err; - } - - if (g->ops.clk.support_clk_freq_controller) { - err = nvgpu_clk_freq_controller_pmu_setup(g); - if (err != 0) { - return err; - } - } - - if (g->ops.clk.support_vf_point && - g->ops.pmu_perf.support_vfe) { - err = nvgpu_clk_vf_point_pmu_setup(g); - if (err != 0) { - return err; - } - } - - err = nvgpu_clk_pmu_vin_load(g); - if (err != 0) { - return err; - } - - if (g->ops.clk.support_clk_freq_domain) { - err = nvgpu_clk_pmu_clk_domains_load(g); - if (err != 0) { - return err; - } - } - - if (g->ops.clk.support_pmgr_domain) { - err = pmgr_domain_pmu_setup(g); - } - - if(g->ops.pmu_perf.support_changeseq) { - err = nvgpu_perf_change_seq_pmu_setup(g); - if (err != 0) { - return err; - } - } - - if (g->ops.pmu_perf.support_vfe) { - err = g->ops.clk.perf_pmu_vfe_load(g); - if (err != 0) { - return err; - } - } - return err; -} +#include "perf_pstate.h" static int pstate_construct_super(struct gk20a *g, struct boardobj **ppboardobj, size_t size, void *args) @@ -462,8 +122,9 @@ static int parse_pstate_entry_5x(struct gk20a *g, struct vbios_pstate_entry_clock_5x *clk_entry; struct nvgpu_clk_domain *clk_domain; - clk_domain = (struct nvgpu_clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX( - &g->clk_pmu->clk_domainobjs->super.super, clkidx); + clk_domain = (struct nvgpu_clk_domain *) + BOARDOBJGRP_OBJ_GET_BY_IDX( + &g->clk_pmu->clk_domainobjs->super.super, clkidx); pclksetinfo = &pstate->clklist.clksetinfo[clkidx]; clk_entry = (struct vbios_pstate_entry_clock_5x *)p; @@ -543,7 +204,7 @@ done: return err; } -static int pstate_sw_setup(struct gk20a *g) +int nvgpu_pmu_perf_pstate_sw_setup(struct gk20a *g) { struct vbios_pstate_header_5x *hdr = NULL; int err = 0; @@ -591,7 +252,7 @@ done: return err; } -struct pstate *pstate_find(struct gk20a *g, u32 num) +struct pstate *nvgpu_pmu_perf_pstate_find(struct gk20a *g, u32 num) { struct pstates *pstates = &(g->perf_pmu->pstatesobjs); struct pstate *pstate; @@ -610,10 +271,10 @@ struct pstate *pstate_find(struct gk20a *g, u32 num) return NULL; } -struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, +struct clk_set_info *nvgpu_pmu_perf_pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num, u32 clkwhich) { - struct pstate *pstate = pstate_find(g, pstate_num); + struct pstate *pstate = nvgpu_pmu_perf_pstate_find(g, pstate_num); struct clk_set_info *info; u32 clkidx; @@ -631,3 +292,4 @@ struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, } return NULL; } + diff --git a/drivers/gpu/nvgpu/common/pmu/pstate/pstate.h b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.h similarity index 87% rename from drivers/gpu/nvgpu/common/pmu/pstate/pstate.h rename to drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.h index 23e4d5aa3..c76d77088 100644 --- a/drivers/gpu/nvgpu/common/pmu/pstate/pstate.h +++ b/drivers/gpu/nvgpu/common/pmu/perf/perf_pstate.h @@ -1,7 +1,7 @@ /* * general p state infrastructure * - * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -21,9 +21,10 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#ifndef NVGPU_PSTATE_PSTATE_H -#define NVGPU_PSTATE_PSTATE_H + +#ifndef NVGPU_PERF_PSTATE_H +#define NVGPU_PERF_PSTATE_H #define CTRL_PERF_PSTATE_TYPE_3X 0x3U -#endif /* NVGPU_PSTATE_PSTATE_H */ +#endif /* NVGPU_PERF_PSTATE_H */ diff --git a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c index 85e4bfbdb..47097f94d 100644 --- a/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c +++ b/drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index 1c978d103..bc5e45a6f 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -39,6 +38,7 @@ #include #include #include +#include /* PMU NS UCODE IMG */ #define NVGPU_PMU_NS_UCODE_IMAGE "gpmu_ucode.bin" diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c new file mode 100644 index 000000000..4526e99ed --- /dev/null +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pstate.c @@ -0,0 +1,501 @@ +/* + * general p state infrastructure + * + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void nvgpu_pmu_pstate_deinit(struct gk20a *g) +{ + pmgr_pmu_free_pmupstate(g); + nvgpu_therm_pmu_free_pmupstate(g); + nvgpu_perf_pmu_free_pmupstate(g); + nvgpu_clk_domain_free_pmupstate(g); + nvgpu_clk_prog_free_pmupstate(g); + nvgpu_clk_vf_point_free_pmupstate(g); + nvgpu_clk_freq_domain_free_pmupstate(g); + nvgpu_clk_freq_controller_free_pmupstate(g); + nvgpu_clk_fll_free_pmupstate(g); + nvgpu_clk_vin_free_pmupstate(g); + nvgpu_clk_free_pmupstate(g); + + if (g->ops.clk.mclk_deinit != NULL) { + g->ops.clk.mclk_deinit(g); + } +} + +static int pmu_pstate_clk_init(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = nvgpu_clk_init_pmupstate(g); + if (err != 0) { + nvgpu_clk_free_pmupstate(g); + return err; + } + + err = nvgpu_clk_domain_init_pmupstate(g); + if (err != 0) { + nvgpu_clk_domain_free_pmupstate(g); + return err; + } + + err = nvgpu_clk_prog_init_pmupstate(g); + if (err != 0) { + nvgpu_clk_prog_free_pmupstate(g); + return err; + } + + err = nvgpu_clk_vf_point_init_pmupstate(g); + if (err != 0) { + nvgpu_clk_vf_point_free_pmupstate(g); + return err; + } + + err = nvgpu_clk_freq_domain_init_pmupstate(g); + if (err != 0) { + nvgpu_clk_freq_domain_free_pmupstate(g); + return err; + } + + err = nvgpu_clk_freq_controller_init_pmupstate(g); + if (err != 0) { + nvgpu_clk_freq_controller_free_pmupstate(g); + return err; + } + + err = nvgpu_clk_vin_init_pmupstate(g); + if (err != 0) { + nvgpu_clk_vin_free_pmupstate(g); + return err; + } + + err = nvgpu_clk_fll_init_pmupstate(g); + if (err != 0) { + nvgpu_clk_fll_free_pmupstate(g); + return err; + } + + return 0; +} + +static int pmu_pstate_init(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = nvgpu_therm_pmu_init_pmupstate(g); + if (err != 0) { + nvgpu_therm_pmu_free_pmupstate(g); + return err; + } + + err = pmu_pstate_clk_init(g); + if (err != 0) { + return err; + } + + err = nvgpu_perf_pmu_init_pmupstate(g); + if (err != 0) { + nvgpu_perf_pmu_free_pmupstate(g); + return err; + } + + err = pmgr_pmu_init_pmupstate(g); + if (err != 0) { + pmgr_pmu_free_pmupstate(g); + return err; + } + + return 0; +} + +static int pmu_pstate_volt_sw_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = nvgpu_volt_rail_sw_setup(g); + if (err != 0) { + return err; + } + + err = nvgpu_volt_dev_sw_setup(g); + if (err != 0) { + return err; + } + + err = nvgpu_volt_policy_sw_setup(g); + if (err != 0) { + return err; + } + + return 0; +} + +static int pmu_pstate_clk_sw_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = nvgpu_clk_vin_sw_setup(g); + if (err != 0) { + nvgpu_clk_vin_free_pmupstate(g); + return err; + } + + err = nvgpu_clk_fll_sw_setup(g); + if (err != 0) { + nvgpu_clk_fll_free_pmupstate(g); + return err; + } + + err = nvgpu_clk_domain_sw_setup(g); + if (err != 0) { + nvgpu_clk_domain_free_pmupstate(g); + return err; + } + + if (g->ops.clk.support_vf_point && + g->ops.pmu_perf.support_vfe) { + err = nvgpu_clk_vf_point_sw_setup(g); + if (err != 0) { + nvgpu_clk_vf_point_free_pmupstate(g); + return err; + } + } + + err = nvgpu_clk_prog_sw_setup(g); + if (err != 0) { + nvgpu_clk_prog_free_pmupstate(g); + return err; + } + + if (g->ops.clk.support_clk_freq_domain) { + err = nvgpu_clk_freq_domain_sw_setup(g); + if (err != 0) { + nvgpu_clk_freq_domain_free_pmupstate(g); + return err; + } + } + + if (g->ops.clk.support_clk_freq_controller) { + err = nvgpu_clk_freq_controller_sw_setup(g); + if (err != 0) { + nvgpu_clk_freq_controller_free_pmupstate(g); + return err; + } + } + + return 0; +} + +static int pmu_pstate_perf_sw_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + if (g->ops.pmu_perf.support_vfe) { + err = nvgpu_vfe_var_sw_setup(g); + if (err != 0) { + return err; + } + + err = nvgpu_vfe_equ_sw_setup(g); + if (err != 0) { + return err; + } + } + + err = nvgpu_pmu_perf_pstate_sw_setup(g); + if (err != 0) { + return err; + } + + if (g->ops.pmu_perf.support_changeseq) { + err = nvgpu_perf_change_seq_sw_setup(g); + if (err != 0) { + return err; + } + } + + return 0; +} + +/*sw setup for pstate components*/ +int nvgpu_pmu_pstate_sw_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = nvgpu_pmu_wait_ready(g); + if (err != 0) { + nvgpu_err(g, "PMU not ready to process pstate requests"); + return err; + } + + err = pmu_pstate_init(g); + if (err != 0) { + nvgpu_err(g, "Pstate init failed"); + return err; + } + + err = pmu_pstate_volt_sw_setup(g); + if (err != 0) { + nvgpu_err(g, "Volt sw setup failed"); + return err; + } + + err = nvgpu_therm_domain_sw_setup(g); + if (err != 0) { + goto err_therm_pmu_init_pmupstate; + } + + err = pmu_pstate_clk_sw_setup(g); + if (err != 0) { + nvgpu_err(g, "Clk sw setup failed"); + return err; + } + + err = pmu_pstate_perf_sw_setup(g); + if (err != 0) { + nvgpu_err(g, "Perf sw setup failed"); + goto err_perf_pmu_init_pmupstate; + } + + if (g->ops.clk.support_pmgr_domain) { + err = pmgr_domain_sw_setup(g); + if (err != 0) { + goto err_pmgr_pmu_init_pmupstate; + } + } + + if (g->ops.clk.support_lpwr_pg) { + err = nvgpu_lpwr_pg_setup(g); + if (err != 0) { + goto err_pmgr_pmu_init_pmupstate; + } + } + + return 0; + +err_pmgr_pmu_init_pmupstate: + pmgr_pmu_free_pmupstate(g); +err_therm_pmu_init_pmupstate: + nvgpu_therm_pmu_free_pmupstate(g); +err_perf_pmu_init_pmupstate: + nvgpu_perf_pmu_free_pmupstate(g); + + return err; +} + +static int pmu_pstate_volt_pmu_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = nvgpu_volt_rail_pmu_setup(g); + if (err != 0) { + return err; + } + + err = nvgpu_volt_dev_pmu_setup(g); + if (err != 0) { + return err; + } + + err = nvgpu_volt_policy_pmu_setup(g); + if (err != 0) { + return err; + } + + err = nvgpu_volt_send_load_cmd_to_pmu(g); + if (err != 0) { + nvgpu_err(g, + "Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.", + err); + return err; + } + + return 0; +} + +static int pmu_pstate_clk_pmu_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + err = nvgpu_clk_domain_pmu_setup(g); + if (err != 0) { + return err; + } + + err = nvgpu_clk_prog_pmu_setup(g); + if (err != 0) { + return err; + } + + err = nvgpu_clk_vin_pmu_setup(g); + if (err != 0) { + return err; + } + + if (g->ops.clk.support_clk_freq_domain) { + err = nvgpu_clk_freq_domain_pmu_setup(g); + if (err != 0) { + return err; + } + } + + err = nvgpu_clk_fll_pmu_setup(g); + if (err != 0) { + return err; + } + + if (g->ops.clk.support_clk_freq_controller) { + err = nvgpu_clk_freq_controller_pmu_setup(g); + if (err != 0) { + return err; + } + } + + if (g->ops.clk.support_vf_point && + g->ops.pmu_perf.support_vfe) { + err = nvgpu_clk_vf_point_pmu_setup(g); + if (err != 0) { + return err; + } + } + + err = nvgpu_clk_pmu_vin_load(g); + if (err != 0) { + return err; + } + + if (g->ops.clk.support_clk_freq_domain) { + err = nvgpu_clk_pmu_clk_domains_load(g); + if (err != 0) { + return err; + } + } + + return 0; +} + +static int pmu_pstate_perf_pmu_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + if (g->ops.pmu_perf.support_vfe) { + err = nvgpu_vfe_var_pmu_setup(g); + if (err != 0) { + return err; + } + + err = nvgpu_vfe_equ_pmu_setup(g); + if (err != 0) { + return err; + } + } + + if (g->ops.pmu_perf.support_changeseq) { + err = nvgpu_perf_change_seq_pmu_setup(g); + if (err != 0) { + return err; + } + } + + return 0; +} + +/*sw setup for pstate components*/ +int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g) +{ + int err; + nvgpu_log_fn(g, " "); + + if (g->ops.clk.mclk_init != NULL) { + err = g->ops.clk.mclk_init(g); + if (err != 0) { + nvgpu_err(g, "failed to set mclk"); + /* Indicate error and continue */ + } + } + + err = pmu_pstate_volt_pmu_setup(g); + if (err != 0) { + nvgpu_err(g, "Failed to send VOLT pmu setup"); + return err; + } + + err = nvgpu_therm_domain_pmu_setup(g); + if (err != 0) { + return err; + } + + err = pmu_pstate_clk_pmu_setup(g); + if (err != 0) { + nvgpu_err(g, "Failed to send CLK pmu setup"); + return err; + } + + err = pmu_pstate_perf_pmu_setup(g); + if (err != 0) { + nvgpu_err(g, "Failed to send Perf pmu setup"); + return err; + } + + if (g->ops.clk.support_pmgr_domain) { + err = pmgr_domain_pmu_setup(g); + } + + if (g->ops.pmu_perf.support_vfe) { + err = g->ops.clk.perf_pmu_vfe_load(g); + if (err != 0) { + return err; + } + } + return err; +} + diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h index f0ad1de7d..e5e77ed56 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h +++ b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h @@ -35,7 +35,9 @@ struct gk20a; #include #include #include -#include +#include +#include +#include #include #define MAX_F_POINTS 256 diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h index 8b5f17c47..5839964a2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pstate.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/perf_pstate.h similarity index 80% rename from drivers/gpu/nvgpu/include/nvgpu/pmu/pstate.h rename to drivers/gpu/nvgpu/include/nvgpu/pmu/perf_pstate.h index 0e750ec68..1c9d22082 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu/pstate.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/perf_pstate.h @@ -21,12 +21,11 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#ifndef NVGPU_PMU_PSTATE_H -#define NVGPU_PMU_PSTATE_H + +#ifndef NVGPU_PMU_PERF_PSTATE_H_ +#define NVGPU_PMU_PERF_PSTATE_H_ #include -#include -#include #define CTRL_PERF_PSTATE_P0 0U #define CTRL_PERF_PSTATE_P5 5U @@ -35,6 +34,8 @@ #define CLK_SET_INFO_MAX_SIZE (32U) struct gk20a; +struct boardobj; +struct boardobjgrp_e32; struct clk_set_info { u32 clkwhich; @@ -63,11 +64,10 @@ struct pstates { struct nvgpu_mutex pstate_mutex; /* protect is_pstate_switch_on */ }; -int gk20a_init_pstate_support(struct gk20a *g); -void gk20a_deinit_pstate_support(struct gk20a *g); -int gk20a_init_pstate_pmu_support(struct gk20a *g); -struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num, - u32 clkwhich); -struct pstate *pstate_find(struct gk20a *g, u32 num); +struct clk_set_info *nvgpu_pmu_perf_pstate_get_clk_set_info(struct gk20a *g, + u32 pstate_num, + u32 clkwhich); +struct pstate *nvgpu_pmu_perf_pstate_find(struct gk20a *g, u32 num); +int nvgpu_pmu_perf_pstate_sw_setup(struct gk20a *g); -#endif /* NVGPU_PMU_PSTATE_H */ +#endif /* NVGPU_PMU_PERF_PSTATE_H_ */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pstate.h b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pstate.h new file mode 100644 index 000000000..ab4db82c6 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pstate.h @@ -0,0 +1,35 @@ +/* + * general p state infrastructure + * + * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef NVGPU_PMU_PSTATE_H +#define NVGPU_PMU_PSTATE_H + +#include + +struct gk20a; + +int nvgpu_pmu_pstate_sw_setup(struct gk20a *g); +void nvgpu_pmu_pstate_deinit(struct gk20a *g); +int nvgpu_pmu_pstate_pmu_setup(struct gk20a *g); + +#endif /* NVGPU_PMU_PSTATE_H */ diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c b/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c index 6e7f4cd5a..5a97f182f 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c index 410d6d409..92f8205a1 100644 --- a/drivers/gpu/nvgpu/os/linux/module.c +++ b/drivers/gpu/nvgpu/os/linux/module.c @@ -49,15 +49,16 @@ #include #include #include +#include #include "common/gr/gr_priv.h" - #include "platform_gk20a.h" #include "sysfs.h" #include "vgpu/vgpu_linux.h" #include "scale.h" #include "pci.h" #include "module.h" + #include "module_usermode.h" #include "intr.h" #include "ioctl.h" @@ -751,7 +752,7 @@ void gk20a_remove_support(struct gk20a *g) g->pmu.remove_support(&g->pmu); if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { - gk20a_deinit_pstate_support(g); + nvgpu_pmu_pstate_deinit(g); } if (g->sec2.remove_support != NULL) {