diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index aa70726a2..8742c4d28 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -450,6 +450,7 @@ nvgpu-y += \ common/sec2/sec2.o \ common/sec2/sec2_allocator.o \ common/sec2/sec2_ipc.o \ + common/sec2/sec2_lsfm.o \ common/sec2/sec2_msg.o \ common/sec2/sec2_queue.o \ common/sec2/sec2_seq.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index f72a99fae..9c88d32ea 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -162,6 +162,7 @@ srcs += common/sim.c \ common/sec2/sec2.c \ common/sec2/sec2_allocator.c \ common/sec2/sec2_ipc.c \ + common/sec2/sec2_lsfm.c \ common/sec2/sec2_msg.c \ common/sec2/sec2_queue.c \ common/sec2/sec2_seq.c \ diff --git a/drivers/gpu/nvgpu/common/sec2/sec2.c b/drivers/gpu/nvgpu/common/sec2/sec2.c index cf31f81f4..ad472088e 100644 --- a/drivers/gpu/nvgpu/common/sec2/sec2.c +++ b/drivers/gpu/nvgpu/common/sec2/sec2.c @@ -109,89 +109,3 @@ int nvgpu_sec2_destroy(struct gk20a *g) return 0; } - -/* Add code below to handle SEC2 RTOS commands */ -/* LSF's bootstrap command */ -static void sec2_handle_lsfm_boot_acr_msg(struct gk20a *g, - struct nv_flcn_msg_sec2 *msg, - void *param, u32 status) -{ - bool *command_ack = param; - - nvgpu_log_fn(g, " "); - - nvgpu_sec2_dbg(g, "reply NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON"); - - nvgpu_sec2_dbg(g, "flcn %d: error code = %x", - msg->msg.acr.msg_flcn.falcon_id, - msg->msg.acr.msg_flcn.error_code); - - *command_ack = true; -} - -static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, - u32 falcon_id, u32 flags) -{ - struct nv_flcn_cmd_sec2 cmd; - bool command_ack; - int err = 0; - size_t tmp_size; - - nvgpu_log_fn(g, " "); - - /* send message to load falcon */ - (void) memset(&cmd, 0, sizeof(struct nv_flcn_cmd_sec2)); - cmd.hdr.unit_id = NV_SEC2_UNIT_ACR; - tmp_size = PMU_CMD_HDR_SIZE + - sizeof(struct nv_sec2_acr_cmd_bootstrap_falcon); - nvgpu_assert(tmp_size <= U64(U8_MAX)); - cmd.hdr.size = U8(tmp_size); - - cmd.cmd.acr.bootstrap_falcon.cmd_type = - NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON; - cmd.cmd.acr.bootstrap_falcon.flags = flags; - cmd.cmd.acr.bootstrap_falcon.falcon_id = falcon_id; - - nvgpu_sec2_dbg(g, "NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON : %x", - falcon_id); - - command_ack = false; - err = nvgpu_sec2_cmd_post(g, &cmd, PMU_COMMAND_QUEUE_HPQ, - sec2_handle_lsfm_boot_acr_msg, &command_ack, U32_MAX); - if (err != 0) { - nvgpu_err(g, "command post failed"); - } - - err = nvgpu_sec2_wait_message_cond(sec2, nvgpu_get_poll_timeout(g), - &command_ack, U8(true)); - if (err != 0) { - nvgpu_err(g, "command ack receive failed"); - } - - return; -} - -int nvgpu_sec2_bootstrap_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, - u32 falcon_id) -{ - int err = 0; - - nvgpu_log_fn(g, " "); - - nvgpu_sec2_dbg(g, "Check SEC2 RTOS is ready else wait"); - err = nvgpu_sec2_wait_message_cond(&g->sec2, nvgpu_get_poll_timeout(g), - &g->sec2.sec2_ready, U8(true)); - if (err != 0){ - nvgpu_err(g, "SEC2 RTOS not ready yet, failed to bootstrap flcn %d", - falcon_id); - goto exit; - } - - nvgpu_sec2_dbg(g, "LS flcn %d bootstrap, blocked call", falcon_id); - sec2_load_ls_falcons(g, sec2, falcon_id, - NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES); - -exit: - nvgpu_sec2_dbg(g, "Done, err-%x", err); - return err; -} diff --git a/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c b/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c new file mode 100644 index 000000000..24a735f06 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sec2/sec2_lsfm.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +/* Add code below to handle SEC2 RTOS commands */ +/* LSF's bootstrap command */ +static void sec2_handle_lsfm_boot_acr_msg(struct gk20a *g, + struct nv_flcn_msg_sec2 *msg, + void *param, u32 status) +{ + bool *command_ack = param; + + nvgpu_log_fn(g, " "); + + nvgpu_sec2_dbg(g, "reply NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON"); + + nvgpu_sec2_dbg(g, "flcn %d: error code = %x", + msg->msg.acr.msg_flcn.falcon_id, + msg->msg.acr.msg_flcn.error_code); + + *command_ack = true; +} + +static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, + u32 falcon_id, u32 flags) +{ + struct nv_flcn_cmd_sec2 cmd; + bool command_ack; + int err = 0; + size_t tmp_size; + + nvgpu_log_fn(g, " "); + + /* send message to load falcon */ + (void) memset(&cmd, 0, sizeof(struct nv_flcn_cmd_sec2)); + cmd.hdr.unit_id = NV_SEC2_UNIT_ACR; + tmp_size = PMU_CMD_HDR_SIZE + + sizeof(struct nv_sec2_acr_cmd_bootstrap_falcon); + nvgpu_assert(tmp_size <= U64(U8_MAX)); + cmd.hdr.size = U8(tmp_size); + + cmd.cmd.acr.bootstrap_falcon.cmd_type = + NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON; + cmd.cmd.acr.bootstrap_falcon.flags = flags; + cmd.cmd.acr.bootstrap_falcon.falcon_id = falcon_id; + + nvgpu_sec2_dbg(g, "NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON : %x", + falcon_id); + + command_ack = false; + err = nvgpu_sec2_cmd_post(g, &cmd, PMU_COMMAND_QUEUE_HPQ, + sec2_handle_lsfm_boot_acr_msg, &command_ack, U32_MAX); + if (err != 0) { + nvgpu_err(g, "command post failed"); + } + + err = nvgpu_sec2_wait_message_cond(sec2, nvgpu_get_poll_timeout(g), + &command_ack, U8(true)); + if (err != 0) { + nvgpu_err(g, "command ack receive failed"); + } +} + +int nvgpu_sec2_bootstrap_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, + u32 falcon_id) +{ + int err = 0; + + nvgpu_log_fn(g, " "); + + nvgpu_sec2_dbg(g, "Check SEC2 RTOS is ready else wait"); + err = nvgpu_sec2_wait_message_cond(&g->sec2, nvgpu_get_poll_timeout(g), + &g->sec2.sec2_ready, U8(true)); + if (err != 0) { + nvgpu_err(g, "SEC2 RTOS not ready yet, failed to bootstrap flcn %d", + falcon_id); + goto exit; + } + + nvgpu_sec2_dbg(g, "LS flcn %d bootstrap, blocked call", falcon_id); + sec2_load_ls_falcons(g, sec2, falcon_id, + NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES); + +exit: + nvgpu_sec2_dbg(g, "Done, err-%x", err); + return err; +} diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2.h index c59e61942..9e3f51956 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2.h @@ -75,10 +75,6 @@ int nvgpu_sec2_cmd_post(struct gk20a *g, struct nv_flcn_cmd_sec2 *cmd, int nvgpu_sec2_wait_message_cond(struct nvgpu_sec2 *sec2, u32 timeout_ms, void *var, u8 val); -/* commands methods*/ -int nvgpu_sec2_bootstrap_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, - u32 falcon_id); - /* sec2 init */ int nvgpu_init_sec2_setup_sw(struct gk20a *g, struct nvgpu_sec2 *sec2); int nvgpu_init_sec2_support(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_acr.h b/drivers/gpu/nvgpu/include/nvgpu/sec2/lsfm.h similarity index 90% rename from drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_acr.h rename to drivers/gpu/nvgpu/include/nvgpu/sec2/lsfm.h index 217f12fc1..18d3112b9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2/lsfm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -20,11 +20,14 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef NVGPU_SEC2_IF_ACR_H -#define NVGPU_SEC2_IF_ACR_H +#ifndef NVGPU_SEC2_BOOTSTRAP_H +#define NVGPU_SEC2_BOOTSTRAP_H #include +struct gk20a; +struct nvgpu_sec2; + /* * ACR Command Types * _BOOT_FALCON @@ -80,7 +83,7 @@ struct nv_sec2_acr_msg_bootstrap_falcon { /* Bootstrapped falcon ID by ACR */ u32 falcon_id; -} ; +}; /* * A union of all ACR Messages. @@ -93,4 +96,7 @@ union nv_sec2_acr_msg { struct nv_sec2_acr_msg_bootstrap_falcon msg_flcn; }; -#endif /* NVGPU_SEC2_IF_ACR_H */ +int nvgpu_sec2_bootstrap_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2, + u32 falcon_id); + +#endif /* NVGPU_SEC2_BOOTSTRAP_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h b/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h index a898a209d..1e1c4d5af 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2/msg.h @@ -23,7 +23,7 @@ #ifndef NVGPU_SEC2_MSG_H #define NVGPU_SEC2_MSG_H -#include +#include #include #include #include diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h b/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h index 415fb7f23..e8d483802 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h @@ -23,7 +23,7 @@ #ifndef NVGPU_SEC2_CMD_IF_H #define NVGPU_SEC2_CMD_IF_H -#include +#include struct nv_flcn_cmd_sec2 { struct pmu_hdr hdr;