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gpu: nvgpu: use nvgpu list APIs instead of linux APIs

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Use nvgpu specific list APIs nvgpu_list_for_each_entry() instead of calling
Linux specific list APIs list_for_each_entry()

Jira NVGPU-444

Change-Id: I3c1fd495ed9e8bebab1f23b6769944373b46059b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612442
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2017-12-06 04:39:59 -08:00
committed by mobile promotions
parent d4c51a7321
commit 6ec7da5eba
8 changed files with 42 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/linux/ioctl_channel.c
View File

@@ -791,8 +791,8 @@ static int gk20a_channel_get_event_data_from_id(struct channel_gk20a *ch,
bool event_found = false;
nvgpu_mutex_acquire(&ch->event_id_list_lock);
list_for_each_entry(local_event_id_data, &ch->event_id_list,
event_id_node) {
nvgpu_list_for_each_entry(local_event_id_data, &ch->event_id_list,
gk20a_event_id_data, event_id_node) {
if (local_event_id_data->event_id == event_id) {
event_found = true;
break;

6
drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c
View File

@@ -692,7 +692,8 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list,
channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch_tsg)) {
nvgpu_set_error_notifier(ch_tsg, err_code);
ch_tsg->has_timedout = true;
@@ -747,7 +748,8 @@ static void vgpu_fifo_set_ctx_mmu_error_ch_tsg(struct gk20a *g,
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list,
channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch_tsg)) {
vgpu_fifo_set_ctx_mmu_error_ch(g, ch_tsg);
gk20a_channel_put(ch_tsg);

9
drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c
View File

@@ -1132,7 +1132,8 @@ static int vgpu_gr_suspend_resume_contexts(struct gk20a *g,
}
n = 0;
list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry)
nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list,
dbg_session_channel_data, ch_entry)
n++;
if (oob_size < n * sizeof(u16)) {
@@ -1145,7 +1146,8 @@ static int vgpu_gr_suspend_resume_contexts(struct gk20a *g,
p = &msg.params.suspend_contexts;
p->num_channels = n;
n = 0;
list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry)
nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list,
dbg_session_channel_data, ch_entry)
oob[n++] = (u16)ch_data->chid;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
@@ -1155,7 +1157,8 @@ static int vgpu_gr_suspend_resume_contexts(struct gk20a *g,
}
if (p->resident_chid != (u16)~0) {
list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list,
dbg_session_channel_data, ch_entry) {
if (ch_data->chid == p->resident_chid) {
channel_fd = ch_data->channel_fd;
break;

8
drivers/gpu/nvgpu/gk20a/channel_gk20a.c
View File

@@ -521,12 +521,12 @@ unbind:
/* unlink all debug sessions */
nvgpu_mutex_acquire(&g->dbg_sessions_lock);
list_for_each_entry_safe(session_data, tmp_s,
&ch->dbg_s_list, dbg_s_entry) {
nvgpu_list_for_each_entry_safe(session_data, tmp_s,
&ch->dbg_s_list, dbg_session_data, dbg_s_entry) {
dbg_s = session_data->dbg_s;
nvgpu_mutex_acquire(&dbg_s->ch_list_lock);
list_for_each_entry_safe(ch_data, tmp,
&dbg_s->ch_list, ch_entry) {
nvgpu_list_for_each_entry_safe(ch_data, tmp, &dbg_s->ch_list,
dbg_session_channel_data, ch_entry) {
if (ch_data->chid == ch->chid)
ch_data->unbind_single_channel(dbg_s, ch_data);
}

26
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1378,7 +1378,7 @@ bool gk20a_fifo_error_tsg(struct gk20a *g,
bool verbose = false;
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch)) {
verbose |= gk20a_fifo_error_ch(g, ch);
gk20a_channel_put(ch);
@@ -1408,7 +1408,7 @@ void gk20a_fifo_set_ctx_mmu_error_tsg(struct gk20a *g,
"TSG %d generated a mmu fault", tsg->tsgid);
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch)) {
gk20a_fifo_set_ctx_mmu_error_ch(g, ch);
gk20a_channel_put(ch);
@@ -1431,7 +1431,7 @@ void gk20a_fifo_abort_tsg(struct gk20a *g, u32 tsgid, bool preempt)
g->ops.fifo.preempt_tsg(g, tsgid);
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch)) {
ch->has_timedout = true;
gk20a_channel_abort_clean_up(ch);
@@ -1932,7 +1932,8 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch,
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list,
channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch_tsg)) {
nvgpu_set_error_notifier(ch_tsg, err_code);
gk20a_channel_put(ch_tsg);
@@ -2127,7 +2128,7 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
* fifo recovery is needed if at least one channel reached the
* maximum timeout without progress (update in gpfifo pointers).
*/
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch)) {
recover = gk20a_channel_update_and_check_timeout(ch,
*ms, &progress);
@@ -2146,7 +2147,8 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
tsg->tsgid, ch->chid);
gk20a_channel_put(ch);
*ms = GRFIFO_TIMEOUT_CHECK_PERIOD_US / 1000;
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list,
channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch)) {
ch->timeout_accumulated_ms = *ms;
gk20a_channel_put(ch);
@@ -2163,7 +2165,8 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
tsg->tsgid, ch->chid);
*ms = ch->timeout_accumulated_ms;
gk20a_channel_put(ch);
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list,
channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch)) {
nvgpu_set_error_notifier(ch,
NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
@@ -2490,7 +2493,8 @@ static void gk20a_fifo_pbdma_fault_rc(struct gk20a *g,
struct channel_gk20a *ch = NULL;
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list,
channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch)) {
nvgpu_set_error_notifier(ch,
error_notifier);
@@ -2650,7 +2654,8 @@ void __locked_fifo_preempt_timeout_rc(struct gk20a *g, u32 id,
"preempt TSG %d timeout", id);
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list,
channel_gk20a, ch_entry) {
if (!gk20a_channel_get(ch))
continue;
nvgpu_set_error_notifier(ch,
@@ -3147,7 +3152,8 @@ static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
/* add runnable channels bound to this TSG */
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list,
channel_gk20a, ch_entry) {
if (!test_bit(ch->chid,
runlist->active_channels))
continue;

9
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -5106,7 +5106,8 @@ static void gk20a_gr_set_error_notifier(struct gk20a *g,
if (gk20a_is_channel_marked_as_tsg(ch)) {
tsg = &g->fifo.tsg[ch->tsgid];
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list,
channel_gk20a, ch_entry) {
if (gk20a_channel_get(ch_tsg)) {
nvgpu_set_error_notifier(ch_tsg,
error_notifier);
@@ -8384,7 +8385,8 @@ int gr_gk20a_suspend_contexts(struct gk20a *g,
nvgpu_mutex_acquire(&dbg_s->ch_list_lock);
list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list,
dbg_session_channel_data, ch_entry) {
ch = g->fifo.channel + ch_data->chid;
ctx_resident = gr_gk20a_suspend_context(ch);
@@ -8424,7 +8426,8 @@ int gr_gk20a_resume_contexts(struct gk20a *g,
goto clean_up;
}
list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list,
dbg_session_channel_data, ch_entry) {
ch = g->fifo.channel + ch_data->chid;
ctx_resident = gr_gk20a_resume_context(ch);

3
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -2084,7 +2084,8 @@ int gr_gp10b_suspend_contexts(struct gk20a *g,
nvgpu_mutex_acquire(&dbg_s->ch_list_lock);
list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch_data, &dbg_s->ch_list,
dbg_session_channel_data, ch_entry) {
ch = g->fifo.channel + ch_data->chid;
ctx_resident = gr_gp10b_suspend_context(ch,

4
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -560,7 +560,7 @@ static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg)
struct channel_gk20a *ch;
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
gv11b_reset_eng_faulted_ch(g, ch->chid);
}
nvgpu_rwsem_up_read(&tsg->ch_list_lock);
@@ -581,7 +581,7 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg)
struct channel_gk20a *ch;
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
gv11b_reset_pbdma_faulted_ch(g, ch->chid);
}
nvgpu_rwsem_up_read(&tsg->ch_list_lock);