From 6f21c665ce71ba37fa889c4dd76a541b21ac244e Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Tue, 16 Jul 2019 15:06:38 -0700 Subject: [PATCH] gpu: nvgpu: fix MISRA errors nvgpu.hal.fifo.ramin Rule 8.6 requires each identifier with external linkage to have exactly one external definitions. This patch fixes rule 8.6 violations in nvgpu/hal/fifo/ramin_gk20a.h. Jira NVGPU-3821 Change-Id: Ie3d6ddea330b9e504bd2157bd853b9db5fb8bfc4 Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/2154375 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sagar Kamble Reviewed-by: Deepak Nibade Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h index c67c9ca5f..d0bbc5c1c 100644 --- a/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h +++ b/drivers/gpu/nvgpu/hal/fifo/ramin_gk20a.h @@ -27,13 +27,16 @@ struct gk20a; struct nvgpu_mem; +u32 gk20a_ramin_base_shift(void); +u32 gk20a_ramin_alloc_size(void); + +#ifdef CONFIG_NVGPU_HAL_NON_FUSA void gk20a_ramin_set_gr_ptr(struct gk20a *g, struct nvgpu_mem *inst_block, u64 gpu_va); void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, u64 pdb_addr, struct nvgpu_mem *pdb_mem); void gk20a_ramin_set_adr_limit(struct gk20a *g, struct nvgpu_mem *inst_block, u64 va_limit); -u32 gk20a_ramin_base_shift(void); -u32 gk20a_ramin_alloc_size(void); +#endif #endif /* NVGPU_RAMIN_GK20A_H */