From 6fa5da61d770ccad756243f7983dbfef95e0c235 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Fri, 13 Dec 2019 12:42:31 -0500 Subject: [PATCH] gpu: nvgpu: use engine_id to access engine_info Generalize use of "engine_id" variable name to index f->engine_info. Jira NVGPU-4511 Change-Id: Ie3bc2c701dc3bab833d6ac134273dd6a102528c2 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2262219 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/engines.c | 117 +++++++++--------- drivers/gpu/nvgpu/common/fifo/runlist.c | 8 +- .../gpu/nvgpu/common/power_features/cg/cg.c | 18 +-- .../gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c | 28 ++--- drivers/gpu/nvgpu/hal/mc/mc_gm20b.c | 12 +- drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c | 6 +- drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c | 16 +-- drivers/gpu/nvgpu/hal/mc/mc_gv100.c | 4 +- drivers/gpu/nvgpu/hal/mc/mc_gv100.h | 2 +- drivers/gpu/nvgpu/hal/mc/mc_gv11b.h | 2 +- drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c | 4 +- drivers/gpu/nvgpu/hal/mc/mc_tu104.c | 14 +-- .../gpu/nvgpu/hal/therm/therm_gv11b_fusa.c | 8 +- drivers/gpu/nvgpu/hal/top/top_gv11b_fusa.c | 2 +- drivers/gpu/nvgpu/include/nvgpu/engines.h | 18 +-- drivers/gpu/nvgpu/include/nvgpu/gops_mc.h | 6 +- userspace/units/cg/nvgpu-cg.c | 18 +-- 17 files changed, 141 insertions(+), 142 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index 268848793..518b54ae6 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -108,7 +108,7 @@ u32 nvgpu_engine_get_ids(struct gk20a *g, struct nvgpu_fifo *f = NULL; u32 instance_cnt = 0; u32 i; - u32 active_engine_id = 0; + u32 engine_id = 0; struct nvgpu_engine_info *info = NULL; if ((g == NULL) || (engine_id_sz == 0U) || @@ -118,12 +118,12 @@ u32 nvgpu_engine_get_ids(struct gk20a *g, f = &g->fifo; for (i = 0U; i < f->num_engines; i++) { - active_engine_id = f->active_engines_list[i]; - info = &f->engine_info[active_engine_id]; + engine_id = f->active_engines_list[i]; + info = &f->engine_info[engine_id]; if (info->engine_enum == engine_enum) { if (instance_cnt < engine_id_sz) { - engine_ids[instance_cnt] = active_engine_id; + engine_ids[instance_cnt] = engine_id; ++instance_cnt; } else { nvgpu_log_info(g, "warning engine_id table sz is small %d", @@ -179,11 +179,11 @@ u32 nvgpu_engine_get_gr_id(struct gk20a *g) return gr_engine_id; } -u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 act_eng_id) +u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 engine_id) { struct nvgpu_engine_info *engine_info = NULL; - engine_info = nvgpu_engine_get_active_eng_info(g, act_eng_id); + engine_info = nvgpu_engine_get_active_eng_info(g, engine_id); if (engine_info != NULL) { return engine_info->intr_mask; } @@ -195,15 +195,15 @@ u32 nvgpu_gr_engine_interrupt_mask(struct gk20a *g) { u32 eng_intr_mask = 0; unsigned int i; - u32 active_engine_id = 0; + u32 engine_id = 0; enum nvgpu_fifo_engine engine_enum; for (i = 0; i < g->fifo.num_engines; i++) { u32 intr_mask; - active_engine_id = g->fifo.active_engines_list[i]; - intr_mask = g->fifo.engine_info[active_engine_id].intr_mask; - engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; + engine_id = g->fifo.active_engines_list[i]; + intr_mask = g->fifo.engine_info[engine_id].intr_mask; + engine_enum = g->fifo.engine_info[engine_id].engine_enum; if (engine_enum != NVGPU_ENGINE_GR) { continue; @@ -219,7 +219,7 @@ u32 nvgpu_ce_engine_interrupt_mask(struct gk20a *g) { u32 eng_intr_mask = 0; unsigned int i; - u32 active_engine_id = 0; + u32 engine_id = 0; enum nvgpu_fifo_engine engine_enum; if ((g->ops.ce.isr_stall == NULL) || @@ -230,9 +230,9 @@ u32 nvgpu_ce_engine_interrupt_mask(struct gk20a *g) for (i = 0; i < g->fifo.num_engines; i++) { u32 intr_mask; - active_engine_id = g->fifo.active_engines_list[i]; - intr_mask = g->fifo.engine_info[active_engine_id].intr_mask; - engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; + engine_id = g->fifo.active_engines_list[i]; + intr_mask = g->fifo.engine_info[engine_id].intr_mask; + engine_enum = g->fifo.engine_info[engine_id].engine_enum; if ((engine_enum == NVGPU_ENGINE_GRCE) || (engine_enum == NVGPU_ENGINE_ASYNC_CE)) { @@ -250,7 +250,7 @@ u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g) struct nvgpu_fifo *f = NULL; u32 i; struct nvgpu_engine_info *engine_info; - u32 active_engine_id = 0; + u32 engine_id = 0; if (g == NULL) { return reset_mask; @@ -259,8 +259,8 @@ u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g) f = &g->fifo; for (i = 0U; i < f->num_engines; i++) { - active_engine_id = f->active_engines_list[i]; - engine_info = &f->engine_info[active_engine_id]; + engine_id = f->active_engines_list[i]; + engine_info = &f->engine_info[engine_id]; engine_enum = engine_info->engine_enum; if ((engine_enum == NVGPU_ENGINE_GRCE) || @@ -290,12 +290,12 @@ int nvgpu_engine_enable_activity_all(struct gk20a *g) int err = 0, ret = 0; for (i = 0; i < g->fifo.num_engines; i++) { - u32 active_engine_id = g->fifo.active_engines_list[i]; + u32 engine_id = g->fifo.active_engines_list[i]; err = nvgpu_engine_enable_activity(g, - &g->fifo.engine_info[active_engine_id]); + &g->fifo.engine_info[engine_id]); if (err != 0) { nvgpu_err(g, - "failed to enable engine %d activity", active_engine_id); + "failed to enable engine %d activity", engine_id); ret = err; } } @@ -410,16 +410,16 @@ int nvgpu_engine_disable_activity_all(struct gk20a *g, { unsigned int i; int err = 0, ret = 0; - u32 active_engine_id; + u32 engine_id; for (i = 0; i < g->fifo.num_engines; i++) { - active_engine_id = g->fifo.active_engines_list[i]; + engine_id = g->fifo.active_engines_list[i]; err = nvgpu_engine_disable_activity(g, - &g->fifo.engine_info[active_engine_id], + &g->fifo.engine_info[engine_id], wait_for_idle); if (err != 0) { nvgpu_err(g, "failed to disable engine %d activity", - active_engine_id); + engine_id); ret = err; break; } @@ -427,13 +427,13 @@ int nvgpu_engine_disable_activity_all(struct gk20a *g, if (err != 0) { while (i-- != 0U) { - active_engine_id = g->fifo.active_engines_list[i]; + engine_id = g->fifo.active_engines_list[i]; err = nvgpu_engine_enable_activity(g, - &g->fifo.engine_info[active_engine_id]); + &g->fifo.engine_info[engine_id]); if (err != 0) { nvgpu_err(g, "failed to re-enable engine %d activity", - active_engine_id); + engine_id); } } } @@ -637,7 +637,7 @@ u32 nvgpu_engine_get_fast_ce_runlist_id(struct gk20a *g) struct nvgpu_fifo *f = NULL; u32 i; struct nvgpu_engine_info *engine_info; - u32 active_engine_id = 0U; + u32 engine_id = 0U; if (g == NULL) { return ce_runlist_id; @@ -646,8 +646,8 @@ u32 nvgpu_engine_get_fast_ce_runlist_id(struct gk20a *g) f = &g->fifo; for (i = 0U; i < f->num_engines; i++) { - active_engine_id = f->active_engines_list[i]; - engine_info = &f->engine_info[active_engine_id]; + engine_id = f->active_engines_list[i]; + engine_info = &f->engine_info[engine_id]; engine_enum = engine_info->engine_enum; /* select last available ASYNC_CE if available */ @@ -694,7 +694,7 @@ bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id) { struct nvgpu_fifo *f = NULL; u32 i; - u32 active_engine_id; + u32 engine_id; struct nvgpu_engine_info *engine_info; if (g == NULL) { @@ -704,9 +704,8 @@ bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id) f = &g->fifo; for (i = 0U; i < f->num_engines; i++) { - active_engine_id = f->active_engines_list[i]; - engine_info = nvgpu_engine_get_active_eng_info(g, - active_engine_id); + engine_id = f->active_engines_list[i]; + engine_info = nvgpu_engine_get_active_eng_info(g, engine_id); if ((engine_info != NULL) && (engine_info->runlist_id == runlist_id)) { return true; @@ -738,20 +737,20 @@ u32 nvgpu_engine_id_to_mmu_fault_id(struct gk20a *g, u32 engine_id) u32 nvgpu_engine_mmu_fault_id_to_engine_id(struct gk20a *g, u32 fault_id) { u32 i; - u32 active_engine_id; + u32 engine_id; struct nvgpu_engine_info *engine_info; struct nvgpu_fifo *f = &g->fifo; for (i = 0U; i < f->num_engines; i++) { - active_engine_id = f->active_engines_list[i]; - engine_info = &g->fifo.engine_info[active_engine_id]; + engine_id = f->active_engines_list[i]; + engine_info = &g->fifo.engine_info[engine_id]; if (engine_info->fault_id == fault_id) { break; } - active_engine_id = NVGPU_INVALID_ENG_ID; + engine_id = NVGPU_INVALID_ENG_ID; } - return active_engine_id; + return engine_id; } u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg) @@ -764,10 +763,10 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg) bool busy; for (i = 0; i < g->fifo.num_engines; i++) { - u32 active_engine_id = g->fifo.active_engines_list[i]; + u32 engine_id = g->fifo.active_engines_list[i]; g->ops.engine_status.read_engine_status_info(g, - active_engine_id, &engine_status); + engine_id, &engine_status); if (nvgpu_engine_status_is_ctxsw_load( &engine_status)) { @@ -785,7 +784,7 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg) ENGINE_STATUS_CTX_ID_TYPE_TSGID) || (!is_tsg && type == ENGINE_STATUS_CTX_ID_TYPE_CHID)) { - engines |= BIT32(active_engine_id); + engines |= BIT32(engine_id); } } } @@ -884,14 +883,14 @@ u32 nvgpu_engine_find_busy_doing_ctxsw(struct gk20a *g, u32 id = U32_MAX; bool is_tsg = false; u32 mailbox2; - u32 act_eng_id = NVGPU_INVALID_ENG_ID; + u32 engine_id = NVGPU_INVALID_ENG_ID; struct nvgpu_engine_status_info engine_status; for (i = 0U; i < g->fifo.num_engines; i++) { bool failing_engine; - act_eng_id = g->fifo.active_engines_list[i]; - g->ops.engine_status.read_engine_status_info(g, act_eng_id, + engine_id = g->fifo.active_engines_list[i]; + g->ops.engine_status.read_engine_status_info(g, engine_id, &engine_status); /* we are interested in busy engines */ @@ -902,7 +901,7 @@ u32 nvgpu_engine_find_busy_doing_ctxsw(struct gk20a *g, nvgpu_engine_status_is_ctxsw(&engine_status); if (!failing_engine) { - act_eng_id = NVGPU_INVALID_ENG_ID; + engine_id = NVGPU_INVALID_ENG_ID; continue; } @@ -933,7 +932,7 @@ u32 nvgpu_engine_find_busy_doing_ctxsw(struct gk20a *g, *id_ptr = id; *is_tsg_ptr = is_tsg; - return act_eng_id; + return engine_id; } u32 nvgpu_engine_get_runlist_busy_engines(struct gk20a *g, u32 runlist_id) @@ -943,16 +942,16 @@ u32 nvgpu_engine_get_runlist_busy_engines(struct gk20a *g, u32 runlist_id) struct nvgpu_engine_status_info engine_status; for (i = 0U; i < f->num_engines; i++) { - u32 act_eng_id = f->active_engines_list[i]; - u32 engine_runlist = f->engine_info[act_eng_id].runlist_id; + u32 engine_id = f->active_engines_list[i]; + u32 engine_runlist = f->engine_info[engine_id].runlist_id; bool engine_busy; - g->ops.engine_status.read_engine_status_info(g, act_eng_id, + g->ops.engine_status.read_engine_status_info(g, engine_id, &engine_status); engine_busy = engine_status.is_busy; if (engine_busy && engine_runlist == runlist_id) { - eng_bitmask |= BIT32(act_eng_id); + eng_bitmask |= BIT32(engine_id); } } @@ -1024,14 +1023,14 @@ u32 nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, u32 mmu_fault_id, u32 *veid) { u32 i; - u32 act_eng_id = INVAL_ID; + u32 engine_id = INVAL_ID; struct nvgpu_engine_info *engine_info; struct nvgpu_fifo *f = &g->fifo; for (i = 0U; i < f->num_engines; i++) { - act_eng_id = f->active_engines_list[i]; - engine_info = &g->fifo.engine_info[act_eng_id]; + engine_id = f->active_engines_list[i]; + engine_info = &g->fifo.engine_info[engine_id]; if (engine_info->engine_enum == NVGPU_ENGINE_GR) { *veid = nvgpu_engine_mmu_fault_id_to_veid(g, @@ -1044,18 +1043,18 @@ u32 nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, break; } } - act_eng_id = INVAL_ID; + engine_id = INVAL_ID; } - return act_eng_id; + return engine_id; } void nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id(struct gk20a *g, - u32 mmu_fault_id, u32 *act_eng_id, u32 *veid, u32 *pbdma_id) + u32 mmu_fault_id, u32 *engine_id, u32 *veid, u32 *pbdma_id) { - *act_eng_id = nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(g, + *engine_id = nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(g, mmu_fault_id, veid); - if (*act_eng_id == INVAL_ID) { + if (*engine_id == INVAL_ID) { *pbdma_id = g->ops.fifo.mmu_fault_id_to_pbdma_id(g, mmu_fault_id); } else { diff --git a/drivers/gpu/nvgpu/common/fifo/runlist.c b/drivers/gpu/nvgpu/common/fifo/runlist.c index 1e8a5c9c4..9988dd156 100644 --- a/drivers/gpu/nvgpu/common/fifo/runlist.c +++ b/drivers/gpu/nvgpu/common/fifo/runlist.c @@ -683,7 +683,7 @@ static void nvgpu_init_runlist_enginfo(struct gk20a *g, struct nvgpu_fifo *f) { struct nvgpu_runlist_info *runlist; struct nvgpu_engine_info *engine_info; - u32 i, active_engine_id, pbdma_id, j; + u32 i, engine_id, pbdma_id, j; nvgpu_log_fn(g, " "); @@ -704,11 +704,11 @@ static void nvgpu_init_runlist_enginfo(struct gk20a *g, struct nvgpu_fifo *f) runlist->runlist_id, runlist->pbdma_bitmask); for (j = 0; j < f->num_engines; j++) { - active_engine_id = f->active_engines_list[j]; - engine_info = &f->engine_info[active_engine_id]; + engine_id = f->active_engines_list[j]; + engine_info = &f->engine_info[engine_id]; if (engine_info->runlist_id == runlist->runlist_id) { - runlist->eng_bitmask |= BIT32(active_engine_id); + runlist->eng_bitmask |= BIT32(engine_id); } } nvgpu_log(g, gpu_dbg_info, "runlist %d : act eng bitmask 0x%x", diff --git a/drivers/gpu/nvgpu/common/power_features/cg/cg.c b/drivers/gpu/nvgpu/common/power_features/cg/cg.c index 10119b2a2..f70ac2fba 100644 --- a/drivers/gpu/nvgpu/common/power_features/cg/cg.c +++ b/drivers/gpu/nvgpu/common/power_features/cg/cg.c @@ -27,8 +27,8 @@ static void nvgpu_cg_set_mode(struct gk20a *g, u32 cgmode, u32 mode_config) { - u32 engine_idx; - u32 active_engine_id = 0; + u32 n; + u32 engine_id = 0; #ifdef CONFIG_NVGPU_NON_FUSA struct nvgpu_engine_info *engine_info = NULL; #endif @@ -36,27 +36,27 @@ static void nvgpu_cg_set_mode(struct gk20a *g, u32 cgmode, u32 mode_config) nvgpu_log_fn(g, " "); - for (engine_idx = 0; engine_idx < f->num_engines; ++engine_idx) { - active_engine_id = f->active_engines_list[engine_idx]; + for (n = 0; n < f->num_engines; n++) { + engine_id = f->active_engines_list[n]; #ifdef CONFIG_NVGPU_NON_FUSA - engine_info = &f->engine_info[active_engine_id]; + engine_info = &f->engine_info[engine_id]; /* gr_engine supports both BLCG and ELCG */ if ((cgmode == BLCG_MODE) && (engine_info->engine_enum == NVGPU_ENGINE_GR)) { g->ops.therm.init_blcg_mode(g, (u32)mode_config, - active_engine_id); + engine_id); break; } else #endif if (cgmode == ELCG_MODE) { g->ops.therm.init_elcg_mode(g, (u32)mode_config, - active_engine_id); + engine_id); } else { nvgpu_err(g, "invalid cg mode %d, config %d for " - "act_eng_id %d", - cgmode, mode_config, active_engine_id); + "engine_id %d", + cgmode, mode_config, engine_id); } } } diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c index aa1308808..0c7bc7739 100644 --- a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c @@ -231,7 +231,7 @@ int gv11b_fifo_preempt_poll_pbdma(struct gk20a *g, u32 tsgid, static int fifo_check_eng_intr_pending(struct gk20a *g, u32 id, u32 eng_stat, u32 ctx_stat, u32 eng_intr_pending, - u32 act_eng_id, u32 *reset_eng_bitmask) + u32 engine_id, u32 *reset_eng_bitmask) { int ret = -EBUSY; @@ -239,7 +239,7 @@ static int fifo_check_eng_intr_pending(struct gk20a *g, u32 id, /* Eng save hasn't started yet. Continue polling */ if (eng_intr_pending != 0U) { /* if eng intr, stop polling */ - *reset_eng_bitmask |= BIT32(act_eng_id); + *reset_eng_bitmask |= BIT32(engine_id); ret = 0; } @@ -250,7 +250,7 @@ static int fifo_check_eng_intr_pending(struct gk20a *g, u32 id, if (id == fifo_engine_status_id_v(eng_stat)) { if (eng_intr_pending != 0U) { /* preemption will not finish */ - *reset_eng_bitmask |= BIT32(act_eng_id); + *reset_eng_bitmask |= BIT32(engine_id); ret = 0; } } else { @@ -263,7 +263,7 @@ static int fifo_check_eng_intr_pending(struct gk20a *g, u32 id, if (id == fifo_engine_status_next_id_v(eng_stat)) { if (eng_intr_pending != 0U) { /* preemption will not finish */ - *reset_eng_bitmask |= BIT32(act_eng_id); + *reset_eng_bitmask |= BIT32(engine_id); ret = 0; } } else { @@ -280,7 +280,7 @@ static int fifo_check_eng_intr_pending(struct gk20a *g, u32 id, } static int gv11b_fifo_preempt_poll_eng(struct gk20a *g, u32 id, - u32 act_eng_id, u32 *reset_eng_bitmask) + u32 engine_id, u32 *reset_eng_bitmask) { struct nvgpu_timeout timeout; u32 delay = POLL_DELAY_MIN_US; @@ -303,7 +303,7 @@ static int gv11b_fifo_preempt_poll_eng(struct gk20a *g, u32 id, ret = -EBUSY; nvgpu_log(g, gpu_dbg_info, "wait preempt act engine id: %u", - act_eng_id); + engine_id); /* Check if ch/tsg has saved off the engine or if ctxsw is hung */ do { if (!nvgpu_platform_is_silicon(g)) { @@ -314,10 +314,10 @@ static int gv11b_fifo_preempt_poll_eng(struct gk20a *g, u32 id, } loop_count++; } - eng_stat = nvgpu_readl(g, fifo_engine_status_r(act_eng_id)); + eng_stat = nvgpu_readl(g, fifo_engine_status_r(engine_id)); ctx_stat = fifo_engine_status_ctx_status_v(eng_stat); - if (g->ops.mc.is_stall_and_eng_intr_pending(g, act_eng_id, + if (g->ops.mc.is_stall_and_eng_intr_pending(g, engine_id, &eng_intr_pending)) { /* * From h/w team @@ -353,7 +353,7 @@ static int gv11b_fifo_preempt_poll_eng(struct gk20a *g, u32 id, "preemption might not finish"); } ret = fifo_check_eng_intr_pending(g, id, eng_stat, ctx_stat, - eng_intr_pending, act_eng_id, + eng_intr_pending, engine_id, reset_eng_bitmask); if (ret == 0) { break; @@ -372,8 +372,8 @@ static int gv11b_fifo_preempt_poll_eng(struct gk20a *g, u32 id, * 3.The engine hangs during CTXSW. */ nvgpu_err(g, "preempt timeout eng: %u ctx_stat: %u tsgid: %u", - act_eng_id, ctx_stat, id); - *reset_eng_bitmask |= BIT32(act_eng_id); + engine_id, ctx_stat, id); + *reset_eng_bitmask |= BIT32(engine_id); } return ret; @@ -387,7 +387,7 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, unsigned long runlist_served_engines; unsigned long bit; u32 pbdma_id; - u32 act_eng_id; + u32 engine_id; u32 runlist_id; int err, ret = 0; u32 tsgid; @@ -417,9 +417,9 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, f->runlist_info[runlist_id]->reset_eng_bitmask = 0U; for_each_set_bit(bit, &runlist_served_engines, f->max_engines) { - act_eng_id = U32(bit); + engine_id = U32(bit); err = gv11b_fifo_preempt_poll_eng(g, - tsgid, act_eng_id, + tsgid, engine_id, &f->runlist_info[runlist_id]->reset_eng_bitmask); if (err != 0 && ret == 0) { ret = err; diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c index fa46d0245..342fcd60e 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c @@ -41,7 +41,7 @@ void gm20b_mc_isr_stall(struct gk20a *g) { u32 mc_intr_0; u32 i; - u32 act_eng_id = 0U; + u32 engine_id = 0U; enum nvgpu_fifo_engine engine_enum; mc_intr_0 = g->ops.mc.intr_stall(g); @@ -49,13 +49,13 @@ void gm20b_mc_isr_stall(struct gk20a *g) nvgpu_log(g, gpu_dbg_intr, "stall intr %08x", mc_intr_0); for (i = 0U; i < g->fifo.num_engines; i++) { - act_eng_id = g->fifo.active_engines_list[i]; + engine_id = g->fifo.active_engines_list[i]; if ((mc_intr_0 & - g->fifo.engine_info[act_eng_id].intr_mask) == 0U) { + g->fifo.engine_info[engine_id].intr_mask) == 0U) { continue; } - engine_enum = g->fifo.engine_info[act_eng_id].engine_enum; + engine_enum = g->fifo.engine_info[engine_id].engine_enum; /* GR Engine */ if (engine_enum == NVGPU_ENGINE_GR) { nvgpu_pg_elpg_protected_call(g, @@ -67,8 +67,8 @@ void gm20b_mc_isr_stall(struct gk20a *g) (engine_enum == NVGPU_ENGINE_ASYNC_CE)) && (g->ops.ce.isr_stall != NULL)) { g->ops.ce.isr_stall(g, - g->fifo.engine_info[act_eng_id].inst_id, - g->fifo.engine_info[act_eng_id].pri_base); + g->fifo.engine_info[engine_id].inst_id, + g->fifo.engine_info[engine_id].pri_base); } } if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c index 3339b6791..2ee86187a 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c @@ -66,7 +66,7 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) u32 ops = 0U; u32 mc_intr_1; u32 i; - u32 act_eng_id = 0U; + u32 engine_id = 0U; enum nvgpu_fifo_engine engine_enum; mc_intr_1 = g->ops.mc.intr_nonstall(g); @@ -78,8 +78,8 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) for (i = 0U; i < g->fifo.num_engines; i++) { struct nvgpu_engine_info *engine_info; - act_eng_id = g->fifo.active_engines_list[i]; - engine_info = &g->fifo.engine_info[act_eng_id]; + engine_id = g->fifo.active_engines_list[i]; + engine_info = &g->fifo.engine_info[engine_id]; if ((mc_intr_1 & engine_info->intr_mask) != 0U) { engine_enum = engine_info->engine_enum; diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c index b57e33f91..688ec9a8b 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c @@ -122,7 +122,7 @@ static void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0) } static void mc_gp10b_isr_stall_engine(struct gk20a *g, - enum nvgpu_fifo_engine engine_enum, u32 act_eng_id) + enum nvgpu_fifo_engine engine_enum, u32 engine_id) { /* GR Engine */ if (engine_enum == NVGPU_ENGINE_GR) { @@ -138,8 +138,8 @@ static void mc_gp10b_isr_stall_engine(struct gk20a *g, (engine_enum == NVGPU_ENGINE_ASYNC_CE)) && (g->ops.ce.isr_stall != NULL)) { g->ops.ce.isr_stall(g, - g->fifo.engine_info[act_eng_id].inst_id, - g->fifo.engine_info[act_eng_id].pri_base); + g->fifo.engine_info[engine_id].inst_id, + g->fifo.engine_info[engine_id].pri_base); } } @@ -183,7 +183,7 @@ void mc_gp10b_isr_stall(struct gk20a *g) { u32 mc_intr_0; u32 i; - u32 act_eng_id = 0U; + u32 engine_id = 0U; enum nvgpu_fifo_engine engine_enum; mc_intr_0 = nvgpu_readl(g, mc_intr_r(0)); @@ -191,14 +191,14 @@ void mc_gp10b_isr_stall(struct gk20a *g) nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0); for (i = 0U; i < g->fifo.num_engines; i++) { - act_eng_id = g->fifo.active_engines_list[i]; + engine_id = g->fifo.active_engines_list[i]; if ((mc_intr_0 & - g->fifo.engine_info[act_eng_id].intr_mask) == 0U) { + g->fifo.engine_info[engine_id].intr_mask) == 0U) { continue; } - engine_enum = g->fifo.engine_info[act_eng_id].engine_enum; - mc_gp10b_isr_stall_engine(g, engine_enum, act_eng_id); + engine_enum = g->fifo.engine_info[engine_id].engine_enum; + mc_gp10b_isr_stall_engine(g, engine_enum, engine_id); } mc_gp10b_isr_stall_secondary_0(g, mc_intr_0); diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gv100.c b/drivers/gpu/nvgpu/hal/mc/mc_gv100.c index f96f92634..1e4a6f205 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gv100.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gv100.c @@ -39,13 +39,13 @@ bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0) return ((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U); } -bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, +bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id, u32 *eng_intr_pending) { u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(0)); u32 stall_intr, eng_intr_mask; - eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, act_eng_id); + eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, engine_id); *eng_intr_pending = mc_intr_0 & eng_intr_mask; stall_intr = mc_intr_pfifo_pending_f() | diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gv100.h b/drivers/gpu/nvgpu/hal/mc/mc_gv100.h index 78ec9c214..b11a65a36 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gv100.h +++ b/drivers/gpu/nvgpu/hal/mc/mc_gv100.h @@ -28,7 +28,7 @@ struct gk20a; bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0); -bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, +bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id, u32 *eng_intr_pending); u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit); diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gv11b.h b/drivers/gpu/nvgpu/hal/mc/mc_gv11b.h index 2f1817070..bd5188b51 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gv11b.h +++ b/drivers/gpu/nvgpu/hal/mc/mc_gv11b.h @@ -28,7 +28,7 @@ struct gk20a; bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0); -bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, +bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id, u32 *eng_intr_pending); bool gv11b_mc_is_mmu_fault_pending(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c index 686e1c39e..8c732f57c 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gv11b_fusa.c @@ -38,13 +38,13 @@ bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) return ((mc_intr_0 & mc_intr_hub_pending_f()) != 0U); } -bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, +bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id, u32 *eng_intr_pending) { u32 mc_intr_0 = nvgpu_readl(g, mc_intr_r(0)); u32 stall_intr, eng_intr_mask; - eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, act_eng_id); + eng_intr_mask = nvgpu_engine_act_interrupt_mask(g, engine_id); *eng_intr_pending = mc_intr_0 & eng_intr_mask; stall_intr = mc_intr_pfifo_pending_f() | diff --git a/drivers/gpu/nvgpu/hal/mc/mc_tu104.c b/drivers/gpu/nvgpu/hal/mc/mc_tu104.c index 40ec42024..646e805c9 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_tu104.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_tu104.c @@ -141,7 +141,7 @@ static void intr_tu104_nonstall_enable(struct gk20a *g) u32 i; u32 nonstall_intr_base = 0; u64 nonstall_intr_mask = 0; - u32 active_engine_id, intr_mask; + u32 engine_id, intr_mask; /* Keep NV_PMC_INTR(1) disabled */ nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), U32_MAX); @@ -158,8 +158,8 @@ static void intr_tu104_nonstall_enable(struct gk20a *g) ctrl_legacy_engine_nonstall_intr_base_vectorid_r()); for (i = 0; i < g->fifo.num_engines; i++) { - active_engine_id = g->fifo.active_engines_list[i]; - intr_mask = g->fifo.engine_info[active_engine_id].intr_mask; + engine_id = g->fifo.active_engines_list[i]; + intr_mask = g->fifo.engine_info[engine_id].intr_mask; nonstall_intr_mask |= U64(intr_mask) << U64(nonstall_intr_base); } @@ -311,7 +311,7 @@ u32 intr_tu104_isr_nonstall(struct gk20a *g) u64 nonstall_intr_mask = 0U; u32 nonstall_intr_mask_lo, nonstall_intr_mask_hi; u32 intr_leaf_reg0, intr_leaf_reg1; - u32 active_engine_id, intr_mask; + u32 engine_id, intr_mask; u32 ops = 0U; intr_leaf_reg0 = nvgpu_func_readl(g, @@ -328,8 +328,8 @@ u32 intr_tu104_isr_nonstall(struct gk20a *g) ctrl_legacy_engine_nonstall_intr_base_vectorid_r()); for (i = 0U; i < g->fifo.num_engines; i++) { - active_engine_id = g->fifo.active_engines_list[i]; - intr_mask = g->fifo.engine_info[active_engine_id].intr_mask; + engine_id = g->fifo.active_engines_list[i]; + intr_mask = g->fifo.engine_info[engine_id].intr_mask; nonstall_intr_mask = U64(intr_mask) << U64(nonstall_intr_base); nonstall_intr_mask_lo = u64_lo32(nonstall_intr_mask); @@ -339,7 +339,7 @@ u32 intr_tu104_isr_nonstall(struct gk20a *g) (nonstall_intr_mask_hi & intr_leaf_reg1) != 0U) { nvgpu_log(g, gpu_dbg_intr, "nonstall intr from engine %d", - active_engine_id); + engine_id); nvgpu_func_writel(g, func_priv_cpu_intr_leaf_r( diff --git a/drivers/gpu/nvgpu/hal/therm/therm_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/therm/therm_gv11b_fusa.c index e51dbcaa5..ca1d16245 100644 --- a/drivers/gpu/nvgpu/hal/therm/therm_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/therm/therm_gv11b_fusa.c @@ -142,7 +142,7 @@ int gv11b_elcg_init_idle_filters(struct gk20a *g) { u32 gate_ctrl, idle_filter; u32 i; - u32 active_engine_id = 0; + u32 engine_id = 0; struct nvgpu_fifo *f = &g->fifo; if (nvgpu_platform_is_simulation(g)) { @@ -152,9 +152,9 @@ int gv11b_elcg_init_idle_filters(struct gk20a *g) nvgpu_log_info(g, "init clock/power gate reg"); for (i = 0; i < f->num_engines; i++) { - active_engine_id = f->active_engines_list[i]; + engine_id = f->active_engines_list[i]; - gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(active_engine_id)); + gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(engine_id)); gate_ctrl = set_field(gate_ctrl, therm_gate_ctrl_eng_idle_filt_exp_m(), therm_gate_ctrl_eng_idle_filt_exp__prod_f()); @@ -167,7 +167,7 @@ int gv11b_elcg_init_idle_filters(struct gk20a *g) gate_ctrl = set_field(gate_ctrl, therm_gate_ctrl_eng_delay_after_m(), therm_gate_ctrl_eng_delay_after__prod_f()); - nvgpu_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); + nvgpu_writel(g, therm_gate_ctrl_r(engine_id), gate_ctrl); } idle_filter = nvgpu_readl(g, therm_fecs_idle_filter_r()); diff --git a/drivers/gpu/nvgpu/hal/top/top_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/top/top_gv11b_fusa.c index d25b8baa5..2735ebfe6 100644 --- a/drivers/gpu/nvgpu/hal/top/top_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/top/top_gv11b_fusa.c @@ -39,7 +39,7 @@ u32 gv11b_top_get_num_lce(struct gk20a *g) } int gv11b_device_info_parse_data(struct gk20a *g, u32 table_entry, u32 *inst_id, - u32 *pri_base, u32 *fault_id) + u32 *pri_base, u32 *fault_id) { if (top_device_info_data_type_v(table_entry) != top_device_info_data_type_enum2_v()) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h index a71785d2f..6bda883eb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/engines.h +++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h @@ -226,16 +226,16 @@ u32 nvgpu_ce_engine_interrupt_mask(struct gk20a *g); * @brief Get intr mask for the h/w engine id. * * @param g [in] The GPU driver struct. - * @param act_eng_id [in] H/w Engine id. + * @param engine_id [in] H/w Engine id. * - * Get pointer to #nvgpu_engine_info for the #act_eng_id. Use this to - * get intr mask for the #act_eng_id. + * Get pointer to #nvgpu_engine_info for the #engine_id. Use this to + * get intr mask for the #engine_id. * - * @return Intr mask for the #act_eng_id. + * @return Intr mask for the #engine_id. * @retval 0 if pointer to #nvgpu_engine_info is NULL for the - * #act_eng_id. + * #engine_id. */ -u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 act_eng_id); +u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 engine_id); /** * @brief Get engine reset mask for CE engines. * @@ -489,7 +489,7 @@ u32 nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, * * @param g [in] The GPU driver struct. * @param mmu_fault_id [in] Mmu fault id. - * @param act_eng_id [in,out] Pointer to store active engine id. + * @param engine_id [in,out] Pointer to store active engine id. * @param veid [in,out] Pointer to store veid. * @param pbdma_id [in,out] Pointer to store pbdma id. * @@ -497,8 +497,8 @@ u32 nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, * If h/w (active) engine id is not #INVAL_ID, call function to get pbdma id for * the engine having fault id as #mmu_fault_id. * - * @return Updated #act_eng_id, #veid and #pbdma_id pointers + * @return Updated #engine_id, #veid and #pbdma_id pointers */ void nvgpu_engine_mmu_fault_id_to_eng_ve_pbdma_id(struct gk20a *g, - u32 mmu_fault_id, u32 *act_eng_id, u32 *veid, u32 *pbdma_id); + u32 mmu_fault_id, u32 *engine_id, u32 *veid, u32 *pbdma_id); #endif /*NVGPU_ENGINE_H*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h b/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h index dfca5d0ee..0516a5b6e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops_mc.h @@ -172,7 +172,7 @@ struct gops_mc { * @brief Check if stalling or engine interrupts are pending. * * @param g [in] The GPU driver struct. - * @param act_eng_id [in] Active engine id. + * @param engine_id [in] Active engine id. * @param eng_intr_pending [out] Indicates if engine interrupt * is pending. * @@ -181,7 +181,7 @@ struct gops_mc { * Steps: * - Read mc_intr_r(#NVGPU_MC_INTR_STALLING) register to get * the interrupts reported. - * - Get the engine interrupt mask corresponding to \a act_eng_id. + * - Get the engine interrupt mask corresponding to \a engine_id. * - Check if the bits for engine interrupt mask are set in the * mc_intr_r(#NVGPU_MC_INTR_STALLING) register by AND'ing values * read in above two steps. Store the result in \a eng_intr_pending. @@ -194,7 +194,7 @@ struct gops_mc { * @return true if stalling or engine interrupt is pending, else false. */ bool (*is_stall_and_eng_intr_pending)(struct gk20a *g, - u32 act_eng_id, u32 *eng_intr_pending); + u32 engine_id, u32 *eng_intr_pending); /** * @brief Reset the HW unit/engine. diff --git a/userspace/units/cg/nvgpu-cg.c b/userspace/units/cg/nvgpu-cg.c index 932644de1..3d6269c91 100644 --- a/userspace/units/cg/nvgpu-cg.c +++ b/userspace/units/cg/nvgpu-cg.c @@ -522,14 +522,14 @@ int test_cg(struct unit_module *m, struct gk20a *g, void *args) static int elcg_add_engine_therm_regs(struct gk20a *g) { u32 i; - u32 active_engine_id = 0; + u32 engine_id = 0; struct nvgpu_fifo *f = &g->fifo; for (i = 0U; i < f->num_engines; i++) { - active_engine_id = f->active_engines_list[i]; + engine_id = f->active_engines_list[i]; if (nvgpu_posix_io_add_reg_space(g, - therm_gate_ctrl_r(active_engine_id), 0x4) != 0) { + therm_gate_ctrl_r(engine_id), 0x4) != 0) { return UNIT_FAIL; } } @@ -540,28 +540,28 @@ static int elcg_add_engine_therm_regs(struct gk20a *g) static void elcg_delete_engine_therm_regs(struct gk20a *g) { u32 i; - u32 active_engine_id = 0; + u32 engine_id = 0; struct nvgpu_fifo *f = &g->fifo; for (i = 0U; i < f->num_engines; i++) { - active_engine_id = f->active_engines_list[i]; + engine_id = f->active_engines_list[i]; nvgpu_posix_io_delete_reg_space(g, - therm_gate_ctrl_r(active_engine_id)); + therm_gate_ctrl_r(engine_id)); } } static int verify_elcg_status(struct gk20a *g, u32 cg_mode) { u32 i; - u32 active_engine_id = 0; + u32 engine_id = 0; struct nvgpu_fifo *f = &g->fifo; int err = UNIT_SUCCESS; u32 gate_r; for (i = 0; i < f->num_engines; i++) { - active_engine_id = f->active_engines_list[i]; - gate_r = nvgpu_readl(g, therm_gate_ctrl_r(active_engine_id)); + engine_id = f->active_engines_list[i]; + gate_r = nvgpu_readl(g, therm_gate_ctrl_r(engine_id)); if (cg_mode == ELCG_RUN) { if (get_field(gate_r,