From 6fb2abb1534c2df020746d7f71e3a818c1fea9c6 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 7 Feb 2019 19:06:40 +0530 Subject: [PATCH] gpu: nvgpu: remove hw_pri_ringmaster_gm20b.h include from gr/config Unit gr/config right now queries gpc_count from priv_ring by directly reading the value from register priv_ring unit now exposes below HAL to get gpc_count g->ops.priv_ring.get_gpc_count() Use this HAL in gr/config unit Jira NVGPU-1879 Change-Id: Ibd3557b7f906690a7ad18f11d02a0a6990b98337 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/2016083 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/config/gr_config.c | 6 +----- drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c | 8 ++++++++ drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h | 2 ++ drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 + drivers/gpu/nvgpu/tu104/hal_tu104.c | 1 + 9 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/config/gr_config.c b/drivers/gpu/nvgpu/common/gr/config/gr_config.c index c5d38c75e..b44dcb432 100644 --- a/drivers/gpu/nvgpu/common/gr/config/gr_config.c +++ b/drivers/gpu/nvgpu/common/gr/config/gr_config.c @@ -24,8 +24,6 @@ #include #include -#include - struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) { struct nvgpu_gr_config *config; @@ -34,7 +32,6 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) u32 pes_tpc_count; u32 pes_heavy_index; u32 gpc_new_skip_mask; - u32 tmp; config = nvgpu_kzalloc(g, sizeof(*config)); if (config == NULL) { @@ -48,8 +45,7 @@ struct nvgpu_gr_config *nvgpu_gr_config_init(struct gk20a *g) config->max_tpc_count = config->max_gpc_count * config->max_tpc_per_gpc_count; - tmp = nvgpu_readl(g, pri_ringmaster_enum_gpc_r()); - config->gpc_count = pri_ringmaster_enum_gpc_count_v(tmp); + config->gpc_count = g->ops.priv_ring.get_gpc_count(g); if (config->gpc_count == 0U) { nvgpu_err(g, "gpc_count==0!"); goto clean_up; diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c index 3e9e7434c..6732ff669 100644 --- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c +++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c @@ -123,3 +123,11 @@ u32 gm20b_priv_ring_enum_ltc(struct gk20a *g) { return gk20a_readl(g, pri_ringmaster_enum_ltc_r()); } + +u32 gm20b_priv_ring_get_gpc_count(struct gk20a *g) +{ + u32 tmp; + + tmp = nvgpu_readl(g, pri_ringmaster_enum_gpc_r()); + return pri_ringmaster_enum_gpc_count_v(tmp); +} diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h index 13d1a8ceb..6bd0a2f92 100644 --- a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h +++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h @@ -29,4 +29,6 @@ void gm20b_priv_ring_enable(struct gk20a *g); void gm20b_priv_set_timeout_settings(struct gk20a *g); u32 gm20b_priv_ring_enum_ltc(struct gk20a *g); +u32 gm20b_priv_ring_get_gpc_count(struct gk20a *g); + #endif /* NVGPU_PRIV_RING_GM20B_H */ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 220743d63..3b69106c6 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -768,6 +768,7 @@ static const struct gpu_ops gm20b_ops = { .set_ppriv_timeout_settings = gm20b_priv_set_timeout_settings, .enum_ltc = gm20b_priv_ring_enum_ltc, + .get_gpc_count = gm20b_priv_ring_get_gpc_count, }, .fuse = { .check_priv_security = gm20b_fuse_check_priv_security, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 3fed4e237..ef00d8213 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -846,6 +846,7 @@ static const struct gpu_ops gp10b_ops = { .set_ppriv_timeout_settings = gm20b_priv_set_timeout_settings, .enum_ltc = gm20b_priv_ring_enum_ltc, + .get_gpc_count = gm20b_priv_ring_get_gpc_count, }, .fuse = { .check_priv_security = gp10b_fuse_check_priv_security, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 3fd986a6e..aeb5106e3 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -1054,6 +1054,7 @@ static const struct gpu_ops gv100_ops = { .set_ppriv_timeout_settings = gm20b_priv_set_timeout_settings, .enum_ltc = gm20b_priv_ring_enum_ltc, + .get_gpc_count = gm20b_priv_ring_get_gpc_count, }, .fuse = { .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index eea110950..3c6b8d7fd 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -982,6 +982,7 @@ static const struct gpu_ops gv11b_ops = { .set_ppriv_timeout_settings = gm20b_priv_set_timeout_settings, .enum_ltc = gm20b_priv_ring_enum_ltc, + .get_gpc_count = gm20b_priv_ring_get_gpc_count, }, .fuse = { .check_priv_security = gp10b_fuse_check_priv_security, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index f0fd64f1e..304ee66f6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -1466,6 +1466,7 @@ struct gpu_ops { void (*decode_error_code)(struct gk20a *g, u32 error_code); void (*set_ppriv_timeout_settings)(struct gk20a *g); u32 (*enum_ltc)(struct gk20a *g); + u32 (*get_gpc_count)(struct gk20a *g); } priv_ring; struct { int (*check_priv_security)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 20a6c237e..55408c997 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -1093,6 +1093,7 @@ static const struct gpu_ops tu104_ops = { .decode_error_code = gp10b_priv_ring_decode_error_code, .set_ppriv_timeout_settings = NULL, .enum_ltc = gm20b_priv_ring_enum_ltc, + .get_gpc_count = gm20b_priv_ring_get_gpc_count, }, .fuse = { .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable,