From 709896c48d1aaa4ba456454fb4991a4443443afc Mon Sep 17 00:00:00 2001 From: Nitin Kumbhar Date: Wed, 15 May 2019 16:08:52 +0530 Subject: [PATCH] gpu: nvgpu: fs_state: fix CERT-C INT violations Error: CERT INT30-C: drivers/gpu/nvgpu/common/gr/fs_state.c:61: cert_violation: Unsigned integer operation "num_tpc_per_gpc * gpc" may wrap. Error: CERT INT30-C: drivers/gpu/nvgpu/common/gr/fs_state.c:70: cert_violation: Unsigned integer operation "(1U << (u32)max_tpc_count) - 1U" may wrap. JIRA NVGPU-3410 Change-Id: If6c12bd6883a8d55d38d128fdef9fab65a600751 Signed-off-by: Nitin Kumbhar Reviewed-on: https://git-master.nvidia.com/r/2119396 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/fs_state.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/fs_state.c b/drivers/gpu/nvgpu/common/gr/fs_state.c index d29f0ef4d..151125c61 100644 --- a/drivers/gpu/nvgpu/common/gr/fs_state.c +++ b/drivers/gpu/nvgpu/common/gr/fs_state.c @@ -21,6 +21,7 @@ */ #include +#include #include #include @@ -58,7 +59,7 @@ static void gr_load_tpc_mask(struct gk20a *g, struct nvgpu_gr_config *config) pes++) { pes_tpc_mask |= nvgpu_gr_config_get_pes_tpc_mask( config, gpc, pes) << - num_tpc_per_gpc * gpc; + nvgpu_secure_mult_u32(num_tpc_per_gpc, gpc); } } @@ -67,11 +68,12 @@ static void gr_load_tpc_mask(struct gk20a *g, struct nvgpu_gr_config *config) fuse_tpc_mask = g->ops.gr.config.get_gpc_tpc_mask(g, config, 0); if ((g->tpc_fs_mask_user != 0U) && (g->tpc_fs_mask_user != fuse_tpc_mask) && - (fuse_tpc_mask == BIT32(max_tpc_count) - U32(1))) { + (fuse_tpc_mask == + nvgpu_secure_sub_u32(BIT32(max_tpc_count), U32(1)))) { val = g->tpc_fs_mask_user; - val &= BIT32(max_tpc_count) - U32(1); + val &= nvgpu_secure_sub_u32(BIT32(max_tpc_count), U32(1)); /* skip tpc to disable the other tpc cause channel timeout */ - val = BIT32(hweight32(val)) - U32(1); + val = nvgpu_secure_sub_u32(BIT32(hweight32(val)), U32(1)); pes_tpc_mask = val; } g->ops.gr.init.tpc_mask(g, 0, pes_tpc_mask); @@ -128,9 +130,10 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config) max_tpc_cnt = nvgpu_gr_config_get_max_tpc_count(config); if ((g->tpc_fs_mask_user != 0U) && - (fuse_tpc_mask == BIT32(max_tpc_cnt) - 1U)) { + (fuse_tpc_mask == + nvgpu_secure_sub_u32(BIT32(max_tpc_cnt), U32(1)))) { u32 val = g->tpc_fs_mask_user; - val &= BIT32(max_tpc_cnt) - U32(1); + val &= nvgpu_secure_sub_u32(BIT32(max_tpc_cnt), U32(1)); tpc_cnt = (u32)hweight32(val); } g->ops.gr.init.cwd_gpcs_tpcs_num(g, gpc_cnt, tpc_cnt);