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gpu: nvgpu: export function definitions across chips

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To avoid duplication of same code across multiple chips, export the
following functions through the corresponding headers for the
consumption of other GPU enabling functions:

- ga10b_gr_intr_report_tpc_sm_rams_ecc_err
- gv11b_gr_intr_report_l1_tag_uncorrected_err
- gv11b_gr_intr_report_l1_tag_corrected_err
- gv11b_gr_intr_report_icache_uncorrected_err

JIRA NVGPU-9075

Change-Id: I927285b6e638479ac52cd5d214711e490e5f151e
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2798371
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Rajesh Devaraj
2022-10-26 17:39:48 +00:00
committed by mobile promotions
parent de0808ea5b
commit 7138e7e673
4 changed files with 14 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -73,5 +73,7 @@ void ga10b_gr_intr_handle_gpc_rrh_hww(struct gk20a *g, u32 gpc, u32 exception);
u32 ga10b_gr_intr_read_pending_interrupts(struct gk20a *g,
struct nvgpu_gr_intr_info *intr_info);
u32 ga10b_gr_intr_enable_mask(struct gk20a *g);
void ga10b_gr_intr_report_tpc_sm_rams_ecc_err(struct gk20a *g,
struct nvgpu_gr_sm_ecc_status *ecc_status, u32 gpc, u32 tpc);
#endif /* NVGPU_GR_INTR_GA10B_H */

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c
View File

@@ -770,7 +770,7 @@ static bool ga10b_gr_intr_sm_icache_ecc_status_errors(struct gk20a *g,
return err_status;
}
static void ga10b_gr_intr_report_tpc_sm_rams_ecc_err(struct gk20a *g,
void ga10b_gr_intr_report_tpc_sm_rams_ecc_err(struct gk20a *g,
struct nvgpu_gr_sm_ecc_status *ecc_status, u32 gpc, u32 tpc)
{
u32 i;

8
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -146,6 +146,12 @@ u32 gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val(void);
bool gv11b_gr_intr_sm_ecc_status_errors(struct gk20a *g,
u32 ecc_status_reg, enum nvgpu_gr_sm_ecc_error_types err_type,
struct nvgpu_gr_sm_ecc_status *ecc_status);
void gv11b_gr_intr_report_l1_tag_uncorrected_err(struct gk20a *g,
struct nvgpu_gr_sm_ecc_status *ecc_status, u32 gpc, u32 tpc);
void gv11b_gr_intr_report_l1_tag_corrected_err(struct gk20a *g,
struct nvgpu_gr_sm_ecc_status *ecc_status, u32 gpc, u32 tpc);
void gv11b_gr_intr_report_icache_uncorrected_err(struct gk20a *g,
struct nvgpu_gr_sm_ecc_status *ecc_status, u32 gpc, u32 tpc);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data);
#endif

6
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
View File

@@ -924,7 +924,7 @@ void gv11b_gr_intr_set_hww_esr_report_mask(struct gk20a *g)
sm_hww_warp_esr_report_mask | get_sm_hww_warp_esr_report_mask());
}
static void gv11b_gr_intr_report_l1_tag_uncorrected_err(struct gk20a *g,
void gv11b_gr_intr_report_l1_tag_uncorrected_err(struct gk20a *g,
struct nvgpu_gr_sm_ecc_status *ecc_status, u32 gpc, u32 tpc)
{
u32 i;
@@ -953,7 +953,7 @@ static void gv11b_gr_intr_report_l1_tag_uncorrected_err(struct gk20a *g,
}
}
static void gv11b_gr_intr_report_l1_tag_corrected_err(struct gk20a *g,
void gv11b_gr_intr_report_l1_tag_corrected_err(struct gk20a *g,
struct nvgpu_gr_sm_ecc_status *ecc_status, u32 gpc, u32 tpc)
{
u32 i;
@@ -1554,7 +1554,7 @@ static void gv11b_gr_intr_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32
gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f());
}
static void gv11b_gr_intr_report_icache_uncorrected_err(struct gk20a *g,
void gv11b_gr_intr_report_icache_uncorrected_err(struct gk20a *g,
struct nvgpu_gr_sm_ecc_status *ecc_status, u32 gpc, u32 tpc)
{
u32 i;