diff --git a/arch/nvgpu-hal-new.yaml b/arch/nvgpu-hal-new.yaml index 577c6f729..7708fdf61 100644 --- a/arch/nvgpu-hal-new.yaml +++ b/arch/nvgpu-hal-new.yaml @@ -102,7 +102,9 @@ ptimer: safe: no owner: Deepak N sources: [ hal/ptimer/ptimer_gp10b.c, - hal/ptimer/ptimer_gp10b.h ] + hal/ptimer/ptimer_gp10b.h, + hal/ptimer/ptimer_gv11b.c, + hal/ptimer/ptimer_gv11b.h ] cg_fusa: safe: yes diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 1aa9d4ce6..c8a848e43 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -704,6 +704,7 @@ nvgpu-y += \ hal/priv_ring/priv_ring_gp10b_fusa.o \ hal/ptimer/ptimer_gk20a_fusa.o \ hal/ptimer/ptimer_gp10b.o \ + hal/ptimer/ptimer_gv11b.o \ hal/therm/therm_gv11b_fusa.o \ hal/top/top_gm20b_fusa.o \ hal/top/top_gv11b_fusa.o diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index e2fae1c98..f7c79e331 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -394,7 +394,8 @@ endif ifeq ($(CONFIG_NVGPU_PROFILER),1) srcs += common/profiler/profiler.c \ common/profiler/pm_reservation.c \ - hal/priv_ring/priv_ring_gv11b.c + hal/priv_ring/priv_ring_gv11b.c \ + hal/ptimer/ptimer_gv11b.c endif ifeq ($(CONFIG_NVGPU_KERNEL_MODE_SUBMIT),1) diff --git a/drivers/gpu/nvgpu/common/profiler/profiler.c b/drivers/gpu/nvgpu/common/profiler/profiler.c index 7a34e07e7..374d14d36 100644 --- a/drivers/gpu/nvgpu/common/profiler/profiler.c +++ b/drivers/gpu/nvgpu/common/profiler/profiler.c @@ -725,6 +725,9 @@ static u32 get_pm_resource_register_range_map_entry_count(struct nvgpu_profiler_ u32 count = 0U; u32 range_count; + /* Account for TYPE_TEST entries added in add_test_range_to_map() */ + count += 2U; + if (prof->reserved[NVGPU_PROFILER_PM_RESOURCE_TYPE_SMPC]) { g->ops.regops.get_smpc_register_ranges(&range_count); count += range_count; @@ -774,6 +777,28 @@ static void add_range_to_map(const struct nvgpu_pm_resource_register_range *rang *map_index = index; } +static void add_test_range_to_map(struct gk20a *g, + struct nvgpu_pm_resource_register_range_map *map, + u32 *map_index, enum nvgpu_pm_resource_hwpm_register_type type) +{ + u32 index = *map_index; + u32 timer0_offset, timer1_offset; + + g->ops.ptimer.get_timer_reg_offsets(&timer0_offset, &timer1_offset); + + map[index].start = timer0_offset; + map[index].end = timer0_offset; + map[index].type = type; + index++; + + map[index].start = timer1_offset; + map[index].end = timer1_offset; + map[index].type = type; + index++; + + *map_index = index; +} + static int nvgpu_profiler_build_regops_allowlist(struct nvgpu_profiler_object *prof) { struct nvgpu_pm_resource_register_range_map *map; @@ -832,6 +857,8 @@ static int nvgpu_profiler_build_regops_allowlist(struct nvgpu_profiler_object *p NVGPU_HWPM_REGISTER_TYPE_HWPM_PMA_CHANNEL); } + add_test_range_to_map(g, map, &map_index, NVGPU_HWPM_REGISTER_TYPE_TEST); + nvgpu_log(g, gpu_dbg_prof, "Allowlist map created successfully for handle %u", prof->prof_handle); @@ -943,7 +970,8 @@ bool nvgpu_profiler_validate_regops_allowlist(struct nvgpu_profiler_object *prof *type = reg_type; } - if (reg_type == NVGPU_HWPM_REGISTER_TYPE_HWPM_PERFMUX) { + if ((reg_type == NVGPU_HWPM_REGISTER_TYPE_HWPM_PERFMUX) || + (reg_type == NVGPU_HWPM_REGISTER_TYPE_TEST)) { return found; } diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index ccf209bc4..de96e5e18 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -87,6 +87,7 @@ #include "hal/fuse/fuse_gp10b.h" #include "hal/ptimer/ptimer_gk20a.h" #include "hal/ptimer/ptimer_gp10b.h" +#include "hal/ptimer/ptimer_gv11b.h" #ifdef CONFIG_NVGPU_DEBUGGER #include "hal/regops/regops_gv11b.h" #include "hal/regops/allowlist_gv11b.h" @@ -1308,6 +1309,9 @@ static const struct gops_ptimer gv11b_ops_ptimer = { #ifdef CONFIG_NVGPU_DEBUGGER .config_gr_tick_freq = gp10b_ptimer_config_gr_tick_freq, #endif +#ifdef CONFIG_NVGPU_PROFILER + .get_timer_reg_offsets = gv11b_ptimer_get_timer_reg_offsets, +#endif }; #if defined(CONFIG_NVGPU_CYCLESTATS) diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index cc9e5b532..158e5a40b 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -73,6 +73,7 @@ #include "hal/fb/intr/fb_intr_tu104.h" #include "hal/ptimer/ptimer_gk20a.h" #include "hal/ptimer/ptimer_gp10b.h" +#include "hal/ptimer/ptimer_gv11b.h" #include "hal/regops/regops_tu104.h" #include "hal/regops/allowlist_tu104.h" #include "hal/func/func_tu104.h" @@ -1381,6 +1382,9 @@ static const struct gops_ptimer tu104_ops_ptimer = { #ifdef CONFIG_NVGPU_DEBUGGER .config_gr_tick_freq = gp10b_ptimer_config_gr_tick_freq, #endif +#ifdef CONFIG_NVGPU_PROFILER + .get_timer_reg_offsets = gv11b_ptimer_get_timer_reg_offsets, +#endif }; #endif diff --git a/drivers/gpu/nvgpu/hal/ptimer/ptimer_gv11b.c b/drivers/gpu/nvgpu/hal/ptimer/ptimer_gv11b.c new file mode 100644 index 000000000..139f0e6f4 --- /dev/null +++ b/drivers/gpu/nvgpu/hal/ptimer/ptimer_gv11b.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "ptimer_gv11b.h" + +#include + +void gv11b_ptimer_get_timer_reg_offsets(u32 *timer0_offset, u32 *timer1_offset) +{ + if (timer0_offset != NULL) { + *timer0_offset = timer_time_0_r(); + } + if (timer1_offset != NULL) { + *timer1_offset = timer_time_1_r(); + } +} diff --git a/drivers/gpu/nvgpu/hal/ptimer/ptimer_gv11b.h b/drivers/gpu/nvgpu/hal/ptimer/ptimer_gv11b.h new file mode 100644 index 000000000..0bd2de17e --- /dev/null +++ b/drivers/gpu/nvgpu/hal/ptimer/ptimer_gv11b.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef PTIMER_GV11B_H +#define PTIMER_GV11B_H + +#ifdef CONFIG_NVGPU_PROFILER + +#include + +void gv11b_ptimer_get_timer_reg_offsets(u32 *timer0_offset, u32 *timer1_offset); + +#endif /* CONFIG_NVGPU_PROFILER */ +#endif /* PTIMER_GV11B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ptimer.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ptimer.h index 1b6e0f2b5..4520f216e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/ptimer.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ptimer.h @@ -93,6 +93,9 @@ struct gops_ptimer { #ifdef CONFIG_NVGPU_DEBUGGER int (*config_gr_tick_freq)(struct gk20a *g); #endif +#ifdef CONFIG_NVGPU_PROFILER + void (*get_timer_reg_offsets)(u32 *timer0_offset, u32 *timer1_offset); +#endif /** @endcond DOXYGEN_SHOULD_SKIP_THIS */ }; diff --git a/drivers/gpu/nvgpu/include/nvgpu/regops_allowlist.h b/drivers/gpu/nvgpu/include/nvgpu/regops_allowlist.h index 888148cc3..39df864ba 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/regops_allowlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/regops_allowlist.h @@ -38,6 +38,7 @@ enum nvgpu_pm_resource_hwpm_register_type { NVGPU_HWPM_REGISTER_TYPE_SMPC, NVGPU_HWPM_REGISTER_TYPE_CAU, NVGPU_HWPM_REGISTER_TYPE_HWPM_PMA_CHANNEL, + NVGPU_HWPM_REGISTER_TYPE_TEST, }; struct nvgpu_pm_resource_register_range_map {