From 715f29ea9fc13e71dd69f00c935c4985748fa783 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Fri, 26 Jul 2019 11:07:04 +0530 Subject: [PATCH] Revert "gpu: nvgpu: handle falcon copy pointer alignment for misra 11.3 deviation" This patch reverts the following commit 13a7ef2cc7303a1564a68249fa74adcd9d07a60d The bios devinit for tu104 encountered the unaligned buffer scenario. However bios devinit functionality is now removed from nvgpu. Other than that there are no firmwares where we expect the input/output buffer addresses to be un-aligned, hence removing the logic added to handle un-aligned addresses. JIRA NVGPU-3271 Change-Id: Ifd24cc5b50b9d2548878436befb2220e7bf02ed4 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/2161735 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/utils/string.c | 10 ---- drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c | 28 +++-------- .../gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c | 48 +++++-------------- drivers/gpu/nvgpu/include/nvgpu/string.h | 11 ----- 4 files changed, 17 insertions(+), 80 deletions(-) diff --git a/drivers/gpu/nvgpu/common/utils/string.c b/drivers/gpu/nvgpu/common/utils/string.c index 0be8b9da8..281193c9c 100644 --- a/drivers/gpu/nvgpu/common/utils/string.c +++ b/drivers/gpu/nvgpu/common/utils/string.c @@ -77,13 +77,3 @@ int nvgpu_strnadd_u32(char *dst, const u32 value, size_t size, u32 radix) return n; } - -bool nvgpu_mem_is_word_aligned(struct gk20a *g, u8 *addr) -{ - if ((unsigned long)addr % 4UL != 0UL) { - nvgpu_log_info(g, "addr (%p) not 4-byte aligned", addr); - return false; - } - - return true; -} diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c index b44005ab4..e49a23a8f 100644 --- a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c +++ b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c @@ -88,17 +88,9 @@ int gk20a_falcon_copy_from_dmem(struct nvgpu_falcon *flcn, nvgpu_writel(g, base_addr + falcon_falcon_dmemc_r(port), src | falcon_falcon_dmemc_aincr_f(1)); - if (unlikely(!nvgpu_mem_is_word_aligned(g, dst))) { - for (i = 0; i < words; i++) { - data = nvgpu_readl(g, - base_addr + falcon_falcon_dmemd_r(port)); - nvgpu_memcpy(&dst[i * 4U], (u8 *)&data, 4); - } - } else { - for (i = 0; i < words; i++) { - dst_u32[i] = nvgpu_readl(g, - base_addr + falcon_falcon_dmemd_r(port)); - } + for (i = 0; i < words; i++) { + dst_u32[i] = nvgpu_readl(g, + base_addr + falcon_falcon_dmemd_r(port)); } if (bytes > 0U) { @@ -135,17 +127,9 @@ int gk20a_falcon_copy_from_imem(struct nvgpu_falcon *flcn, u32 src, falcon_falcon_imemc_blk_f(blk) | falcon_falcon_dmemc_aincr_f(1)); - if (unlikely(!nvgpu_mem_is_word_aligned(g, dst))) { - for (i = 0; i < words; i++) { - data = nvgpu_readl(g, - base_addr + falcon_falcon_imemd_r(port)); - nvgpu_memcpy(&dst[i * 4U], (u8 *)&data, 4); - } - } else { - for (i = 0; i < words; i++) { - dst_u32[i] = nvgpu_readl(g, - base_addr + falcon_falcon_imemd_r(port)); - } + for (i = 0; i < words; i++) { + dst_u32[i] = nvgpu_readl(g, + base_addr + falcon_falcon_imemd_r(port)); } if (bytes > 0U) { diff --git a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c index 0f2a04162..42cb94da3 100644 --- a/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c @@ -149,17 +149,9 @@ int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn, nvgpu_writel(g, base_addr + falcon_falcon_dmemc_r(port), dst | falcon_falcon_dmemc_aincw_f(1)); - if (unlikely(!nvgpu_mem_is_word_aligned(g, src))) { - for (i = 0; i < words; i++) { - nvgpu_memcpy((u8 *)&data, &src[i * 4U], 4); - nvgpu_writel(g, base_addr + falcon_falcon_dmemd_r(port), - data); - } - } else { - for (i = 0; i < words; i++) { - nvgpu_writel(g, base_addr + falcon_falcon_dmemd_r(port), - src_u32[i]); - } + for (i = 0; i < words; i++) { + nvgpu_writel(g, base_addr + falcon_falcon_dmemd_r(port), + src_u32[i]); } if (bytes > 0U) { @@ -186,7 +178,6 @@ int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, u32 base_addr = flcn->flcn_base; u32 *src_u32 = (u32 *)src; u32 words = 0; - u32 data = 0; u32 blk = 0; u32 i = 0; @@ -205,34 +196,17 @@ int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, falcon_falcon_imemc_aincw_f(1) | falcon_falcon_imemc_secure_f(sec ? 1U : 0U)); - if (unlikely(!nvgpu_mem_is_word_aligned(g, src))) { - for (i = 0U; i < words; i++) { - if (i % 64U == 0U) { - /* tag is always 256B aligned */ - nvgpu_writel(g, - base_addr + falcon_falcon_imemt_r(0), - tag); - tag++; - } - - nvgpu_memcpy((u8 *)&data, &src[i * 4U], 4); + for (i = 0U; i < words; i++) { + if (i % 64U == 0U) { + /* tag is always 256B aligned */ nvgpu_writel(g, - base_addr + falcon_falcon_imemd_r(port), - data); + base_addr + falcon_falcon_imemt_r(0), + tag); + tag++; } - } else { - for (i = 0U; i < words; i++) { - if (i % 64U == 0U) { - /* tag is always 256B aligned */ - nvgpu_writel(g, - base_addr + falcon_falcon_imemt_r(0), - tag); - tag++; - } - nvgpu_writel(g, base_addr + falcon_falcon_imemd_r(port), - src_u32[i]); - } + nvgpu_writel(g, base_addr + falcon_falcon_imemd_r(port), + src_u32[i]); } /* WARNING : setting remaining bytes in block to 0x0 */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/string.h b/drivers/gpu/nvgpu/include/nvgpu/string.h index be1700e4a..310787133 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/string.h +++ b/drivers/gpu/nvgpu/include/nvgpu/string.h @@ -29,8 +29,6 @@ #include #endif -struct gk20a; - /** * nvgpu_memcpy - Copy memory buffer * @@ -65,13 +63,4 @@ int nvgpu_memcmp(const u8 *b1, const u8 *b2, size_t n); */ int nvgpu_strnadd_u32(char *dst, const u32 value, size_t size, u32 radix); -/** - * nvgpu_mem_is_word_aligned - Check that memory address is word (4-byte) - * aligned. - * - * @g - struct gk20a. - * @addr - memory address. - */ -bool nvgpu_mem_is_word_aligned(struct gk20a *g, u8 *addr); - #endif /* NVGPU_STRING_H */