nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 01:50:07 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: vgpu: add set mmu debug mode support

Browse Source 
JIRA VFND-1005
Bug 1594604

Change-Id: Ic159a1aff9cee508194f1f5dff7a16eb0e47ad64
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/833498
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Richard Zhao
2015-11-12 12:13:30 -08:00
committed by Vladislav Buzov
parent 3298a8befb
commit 71c8d62657
2 changed files with 25 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/nvgpu/vgpu/mm_vgpu.c
View File

@@ -531,8 +531,26 @@ static void vgpu_mm_tlb_invalidate(struct vm_gk20a *vm)
WARN_ON(err || msg.ret); WARN_ON(err || msg.ret);
} }
static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
{
struct gk20a_platform *platform = gk20a_get_platform(g->dev);
struct tegra_vgpu_cmd_msg msg;
struct tegra_vgpu_mmu_debug_mode *p = &msg.params.mmu_debug_mode;
int err;
gk20a_dbg_fn("");
msg.cmd = TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE;
msg.handle = platform->virt_handle;
p->enable = (u32)enable;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
WARN_ON(err || msg.ret);
}
void vgpu_init_mm_ops(struct gpu_ops *gops) void vgpu_init_mm_ops(struct gpu_ops *gops)
{ {
gops->mm.is_debug_mode_enabled = NULL;
gops->mm.set_debug_mode = vgpu_mm_mmu_set_debug_mode;
gops->mm.gmmu_map = vgpu_locked_gmmu_map; gops->mm.gmmu_map = vgpu_locked_gmmu_map;
gops->mm.gmmu_unmap = vgpu_locked_gmmu_unmap; gops->mm.gmmu_unmap = vgpu_locked_gmmu_unmap;
gops->mm.vm_remove = vgpu_vm_remove_support; gops->mm.vm_remove = vgpu_vm_remove_support;

8
include/linux/tegra_vgpu.h
View File

@@ -70,7 +70,8 @@ enum {
TEGRA_VGPU_CMD_ZBC_SET_TABLE, TEGRA_VGPU_CMD_ZBC_SET_TABLE,
TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, TEGRA_VGPU_CMD_ZBC_QUERY_TABLE,
TEGRA_VGPU_CMD_AS_MAP_EX, TEGRA_VGPU_CMD_AS_MAP_EX,
TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS,
TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE
}; };
struct tegra_vgpu_connect_params { struct tegra_vgpu_connect_params {
@@ -259,6 +260,10 @@ struct tegra_vgpu_gr_bind_ctxsw_buffers_params {
u32 mode; u32 mode;
}; };
struct tegra_vgpu_mmu_debug_mode {
u32 enable;
};
struct tegra_vgpu_cmd_msg { struct tegra_vgpu_cmd_msg {
u32 cmd; u32 cmd;
int ret; int ret;
@@ -283,6 +288,7 @@ struct tegra_vgpu_cmd_msg {
struct tegra_vgpu_zbc_set_table_params zbc_set_table; struct tegra_vgpu_zbc_set_table_params zbc_set_table;
struct tegra_vgpu_zbc_query_table_params zbc_query_table; struct tegra_vgpu_zbc_query_table_params zbc_query_table;
struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers;
struct tegra_vgpu_mmu_debug_mode mmu_debug_mode;
char padding[192]; char padding[192];
} params; } params;
}; };