gpu: nvgpu: MSCG support

- Added enable_mscg, mscg_enabled & mscg_stat flags,
  mscg_enabled flag can be used to controll
  mscg enable/disable at runtime along with mscg_stat flag.
- Added defines & interface to support ms/mclk-change/post-init-param
- Added defines for lpwr tables read  from vbios.
- HAL to support post init param which is require
  to setup clockgating interface in PMU & interfaces used during
  mscg state machine.
- gk20a_pmu_pg_global_enable() can be called when pg support
  required to enable/disable, this also checks & wait
  if pstate switch is in progress till it complets
- pg_mutex to protect PG-RPPG/MSCG enable/disable

JIRA DNVGPU-71

Change-Id: If312cefc888a4de0a5c96898baeaac1a76e53e46
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247554
(cherry picked from commit e6c94948b8058ba642ea56677ad798fc56b8a28a)
Reviewed-on: http://git-master/r/1270971
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -610,6 +610,9 @@ struct gpu_ops {
 		u32 (*pmu_pg_supported_engines_list)(struct gk20a *g);
 		u32 (*pmu_pg_engines_feature_list)(struct gk20a *g,
 			u32 pg_engine_id);
+		int (*pmu_lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
+		int (*pmu_lpwr_disable_pg)(struct gk20a *g, bool pstate_lock);
+		u32 (*pmu_pg_param_post_init)(struct gk20a *g);
 		int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd)
 			(struct gk20a *g, u32 mask);
 		void (*dump_secure_fuses)(struct gk20a *g);
@@ -847,6 +850,7 @@ struct gk20a {
 	bool elcg_enabled;
 	bool elpg_enabled;
 	bool aelpg_enabled;
+	bool mscg_enabled;
 	bool forced_idle;
 	bool forced_reset;
 	bool allow_all;