From 72151c579ff5a07bb5276399d70dde873ff1ebe0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Konsta=20H=C3=B6ltt=C3=A4?= Date: Fri, 3 Apr 2020 08:57:59 +0300 Subject: [PATCH] gpu: nvgpu: hide priv cmd queue type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move struct priv_cmd_queue to priv_cmdbuf.c so that its definition does not need to be visible to all users of channel.h. This also forces it to be separately allocated (during channel init time). While at it, rename the functions to allocate and free priv cmdbuf queues now that they're not in channel.c anymore. A private command buffer queue is a piece of dma memory from which entries for incr and wait command lists are suballocated. As the name implies, it's a queue; allocations and frees of the bufs must happen in certain order. Jira NVGPU-4548 Change-Id: I1b47029f3a478e1942f24292918b7b59a5d91528 Signed-off-by: Konsta Hölttä Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323147 (cherry picked from commit 1fcf9b04275f44638059c0147dc16c1dc6956510) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328407 Reviewed-by: automaticguardword Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Alex Waterman Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/channel.c | 6 +-- drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c | 37 ++++++++++++------- drivers/gpu/nvgpu/include/nvgpu/channel.h | 10 +---- drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h | 4 +- 4 files changed, 31 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index b2cb0fa85..4cb7e92b5 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c @@ -222,7 +222,7 @@ static void channel_kernelmode_deinit(struct nvgpu_channel *ch) #endif (void) memset(&ch->gpfifo, 0, sizeof(struct gpfifo_desc)); - channel_free_priv_cmd_q(ch); + nvgpu_free_priv_cmdbuf_queue(ch); /* free pre-allocated resources, if applicable */ if (nvgpu_channel_is_prealloc_enabled(ch)) { @@ -606,7 +606,7 @@ static int channel_setup_kernelmode(struct nvgpu_channel *c, } } - err = channel_alloc_priv_cmdbuf(c, args->num_inflight_jobs); + err = nvgpu_alloc_priv_cmdbuf_queue(c, args->num_inflight_jobs); if (err != 0) { goto clean_up_prealloc; } @@ -619,7 +619,7 @@ static int channel_setup_kernelmode(struct nvgpu_channel *c, return 0; clean_up_priv_cmd: - channel_free_priv_cmd_q(c); + nvgpu_free_priv_cmdbuf_queue(c); clean_up_prealloc: if (nvgpu_channel_is_deterministic(c) && args->num_inflight_jobs != 0U) { diff --git a/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c b/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c index cdcf2ef55..3ced083f3 100644 --- a/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c +++ b/drivers/gpu/nvgpu/common/fifo/priv_cmdbuf.c @@ -30,14 +30,21 @@ #include #include -/* allocate private cmd buffer. +struct priv_cmd_queue { + struct nvgpu_mem mem; + u32 size; /* num of entries in words */ + u32 put; /* put for priv cmd queue */ + u32 get; /* get for priv cmd queue */ +}; + +/* allocate private cmd buffer queue. used for inserting commands before/after user submitted buffers. */ -int channel_alloc_priv_cmdbuf(struct nvgpu_channel *ch, +int nvgpu_alloc_priv_cmdbuf_queue(struct nvgpu_channel *ch, u32 num_in_flight) { struct gk20a *g = ch->g; struct vm_gk20a *ch_vm = ch->vm; - struct priv_cmd_queue *q = &ch->priv_cmd_q; + struct priv_cmd_queue *q; u64 size, tmp_size; int err = 0; bool gpfifo_based = false; @@ -80,42 +87,46 @@ int channel_alloc_priv_cmdbuf(struct nvgpu_channel *ch, nvgpu_assert(tmp_size <= U32_MAX); size = (u32)tmp_size; + q = nvgpu_kzalloc(g, sizeof(*q)); + err = nvgpu_dma_alloc_map_sys(ch_vm, size, &q->mem); if (err != 0) { nvgpu_err(g, "%s: memory allocation failed", __func__); - goto clean_up; + goto err_free_buf; } tmp_size = q->mem.size / sizeof(u32); nvgpu_assert(tmp_size <= U32_MAX); q->size = (u32)tmp_size; - return 0; + ch->priv_cmd_q = q; -clean_up: - channel_free_priv_cmd_q(ch); + return 0; +err_free_buf: + nvgpu_kfree(g, q); return err; } -void channel_free_priv_cmd_q(struct nvgpu_channel *ch) +void nvgpu_free_priv_cmdbuf_queue(struct nvgpu_channel *ch) { struct vm_gk20a *ch_vm = ch->vm; - struct priv_cmd_queue *q = &ch->priv_cmd_q; + struct priv_cmd_queue *q = ch->priv_cmd_q; - if (q->size == 0U) { + if (q == NULL) { return; } nvgpu_dma_unmap_free(ch_vm, &q->mem); + nvgpu_kfree(ch->g, q); - (void) memset(q, 0, sizeof(struct priv_cmd_queue)); + ch->priv_cmd_q = NULL; } /* allocate a cmd buffer with given size. size is number of u32 entries */ int nvgpu_channel_alloc_priv_cmdbuf(struct nvgpu_channel *c, u32 orig_size, struct priv_cmd_entry *e) { - struct priv_cmd_queue *q = &c->priv_cmd_q; + struct priv_cmd_queue *q = c->priv_cmd_q; u32 free_count; u32 size = orig_size; @@ -191,7 +202,7 @@ void nvgpu_channel_free_priv_cmd_entry(struct nvgpu_channel *c, void nvgpu_channel_update_priv_cmd_q_and_free_entry( struct nvgpu_channel *ch, struct priv_cmd_entry *e) { - struct priv_cmd_queue *q = &ch->priv_cmd_q; + struct priv_cmd_queue *q = ch->priv_cmd_q; struct gk20a *g = ch->g; if (e == NULL) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h index cdef0544a..cb77c754d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h @@ -46,6 +46,7 @@ struct nvgpu_gpfifo_userdata; struct nvgpu_gr_subctx; struct nvgpu_gr_ctx; struct nvgpu_debug_context; +struct priv_cmd_queue; struct priv_cmd_entry; /** @@ -251,13 +252,6 @@ struct notification { u16 status; }; -struct priv_cmd_queue { - struct nvgpu_mem mem; - u32 size; /* num of entries in words */ - u32 put; /* put for priv cmd queue */ - u32 get; /* get for priv cmd queue */ -}; - struct nvgpu_channel_job { struct nvgpu_mapped_buf **mapped_buffers; u32 num_mapped_buffers; @@ -411,7 +405,7 @@ struct nvgpu_channel { #ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT struct nvgpu_channel_joblist joblist; struct gpfifo_desc gpfifo; - struct priv_cmd_queue priv_cmd_q; + struct priv_cmd_queue *priv_cmd_q; struct nvgpu_channel_sync *sync; /* for job cleanup handling in the background worker */ struct nvgpu_list_node worker_item; diff --git a/drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h b/drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h index 2c98c8482..161dea16c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h +++ b/drivers/gpu/nvgpu/include/nvgpu/priv_cmdbuf.h @@ -38,8 +38,8 @@ struct priv_cmd_entry { u32 size; /* in words */ }; -int channel_alloc_priv_cmdbuf(struct nvgpu_channel *ch, u32 num_in_flight); -void channel_free_priv_cmd_q(struct nvgpu_channel *ch); +int nvgpu_alloc_priv_cmdbuf_queue(struct nvgpu_channel *ch, u32 num_in_flight); +void nvgpu_free_priv_cmdbuf_queue(struct nvgpu_channel *ch); int nvgpu_channel_alloc_priv_cmdbuf(struct nvgpu_channel *c, u32 orig_size, struct priv_cmd_entry *e);