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gpu: nvgpu: Disable GM20b GPCPLL SYNC mode

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Disabled GPCPLL SYNC mode after GM20b is switched to bypass clock when
powering down GPU.

Bug 1450787

Change-Id: Ifaec2c562e51c0ae1328b7505faafd19607a77f2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/456504
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
This commit is contained in:
Alex Frid
2014-08-13 20:37:06 -07:00
committed by Dan Willemsen
parent 08dc7c3584
commit 7252af5389
1 changed files with 6 additions and 0 deletions
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6
drivers/gpu/nvgpu/gm20b/clk_gm20b.c
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@@ -493,6 +493,12 @@ static int clk_disable_gpcpll(struct gk20a *g, int allow_slide)
trim_sys_sel_vco_gpc2clk_out_bypass_f()); trim_sys_sel_vco_gpc2clk_out_bypass_f());
gk20a_writel(g, trim_sys_sel_vco_r(), cfg); gk20a_writel(g, trim_sys_sel_vco_r(), cfg);
/* clear SYNC_MODE before disabling PLL */
cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(),
trim_sys_gpcpll_cfg_sync_mode_disable_f());
gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg);
/* disable PLL */ /* disable PLL */
cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r());
cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(), cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(),