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gpu: nvgpu: Add HAL op for PMU reset

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Sequence to reset PMU is different for iGPU and dGPU. Specialize
and implement iGPU version.

Change-Id: I5b9ff2c018a736bc9e27b90d0942c52706b12a12
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1150540
This commit is contained in:
Terje Bergstrom
2016-05-19 09:28:30 -07:00
parent a21e56d584
commit 72ae2dedf5
4 changed files with 11 additions and 0 deletions
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1
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -533,6 +533,7 @@ struct gpu_ops {
int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd)
(struct gk20a *g, u32 mask); (struct gk20a *g, u32 mask);
void (*dump_secure_fuses)(struct gk20a *g); void (*dump_secure_fuses)(struct gk20a *g);
int (*reset)(struct gk20a *g);
u32 lspmuwprinitdone; u32 lspmuwprinitdone;
u32 lsfloadedfalconid; u32 lsfloadedfalconid;
bool fecsbootstrapdone; bool fecsbootstrapdone;

8
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
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@@ -2757,6 +2757,13 @@ static void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr)
gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr);
} }
int gk20a_pmu_reset(struct gk20a *g)
{
gk20a_reset(g, mc_enable_pwr_enabled_f());
return 0;
}
void gk20a_init_pmu_ops(struct gpu_ops *gops) void gk20a_init_pmu_ops(struct gpu_ops *gops)
{ {
gops->pmu.prepare_ucode = gk20a_prepare_ucode; gops->pmu.prepare_ucode = gk20a_prepare_ucode;
@@ -2770,6 +2777,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
gops->pmu.pmu_pg_grinit_param = NULL; gops->pmu.pmu_pg_grinit_param = NULL;
gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
gops->pmu.dump_secure_fuses = NULL; gops->pmu.dump_secure_fuses = NULL;
gops->pmu.reset = gk20a_pmu_reset;
} }
int gk20a_init_pmu_support(struct gk20a *g) int gk20a_init_pmu_support(struct gk20a *g)

1
drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
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@@ -1426,5 +1426,6 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
void *param, u32 handle, u32 status); void *param, u32 handle, u32 status);
void gk20a_pmu_elpg_statistics(struct gk20a *g, void gk20a_pmu_elpg_statistics(struct gk20a *g,
u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt);
int gk20a_pmu_reset(struct gk20a *g);
#endif /*__PMU_GK20A_H__*/ #endif /*__PMU_GK20A_H__*/

1
drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
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@@ -323,4 +323,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops)
gops->pmu.pmu_pg_grinit_param = NULL; gops->pmu.pmu_pg_grinit_param = NULL;
gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b; gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b;
gops->pmu.reset = gk20a_pmu_reset;
} }