diff --git a/drivers/gpu/nvgpu/common/gr/ctx.c b/drivers/gpu/nvgpu/common/gr/ctx.c index 1aadf9671..cd9e8f89f 100644 --- a/drivers/gpu/nvgpu/common/gr/ctx.c +++ b/drivers/gpu/nvgpu/common/gr/ctx.c @@ -489,7 +489,9 @@ void nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, nvgpu_gr_global_ctx_load_local_golden_image(g, local_golden_image, mem); +#ifdef CONFIG_NVGPU_HAL_NON_FUSA g->ops.gr.ctxsw_prog.init_ctxsw_hdr_data(g, mem); +#endif #ifdef CONFIG_NVGPU_DEBUGGER if ((g->ops.gr.ctxsw_prog.set_cde_enabled != NULL) && cde) { @@ -506,8 +508,10 @@ void nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA)); #endif +#ifdef CONFIG_NVGPU_HAL_NON_FUSA /* disable verif features */ g->ops.gr.ctxsw_prog.disable_verif_features(g, mem); +#endif #ifdef CONFIG_NVGPU_DEBUGGER if (g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies != diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c index 836d65f23..8131a0126 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c @@ -120,3 +120,27 @@ void gm20b_ctxsw_prog_set_ts_buffer_ptr(struct gk20a *g, aperture_mask); } #endif + +#ifdef CONFIG_NVGPU_HAL_NON_FUSA +void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, + struct nvgpu_mem *ctx_mem) +{ + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_num_save_ops_o(), 0); + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_num_restore_ops_o(), 0); +} + +void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, + struct nvgpu_mem *ctx_mem) +{ + u32 data; + + data = nvgpu_mem_rd(g, ctx_mem, ctxsw_prog_main_image_misc_options_o()); + + data = data & ~ctxsw_prog_main_image_misc_options_verif_features_m(); + data = data | ctxsw_prog_main_image_misc_options_verif_features_disabled_f(); + + nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_misc_options_o(), data); +} +#endif diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h index 164a606c4..517ae10e5 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h @@ -34,17 +34,17 @@ void gm20b_ctxsw_prog_set_patch_count(struct gk20a *g, struct nvgpu_mem *ctx_mem, u32 count); void gm20b_ctxsw_prog_set_patch_addr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); -void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, - struct nvgpu_mem *ctx_mem); #if defined(CONFIG_NVGPU_SET_FALCON_ACCESS_MAP) void gm20b_ctxsw_prog_set_config_mode_priv_access_map(struct gk20a *g, struct nvgpu_mem *ctx_mem, bool allow_all); void gm20b_ctxsw_prog_set_addr_priv_access_map(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); #endif +#if defined(CONFIG_NVGPU_HAL_NON_FUSA) +void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, + struct nvgpu_mem *ctx_mem); void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, struct nvgpu_mem *ctx_mem); -#if defined(CONFIG_NVGPU_HAL_NON_FUSA) void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g, struct nvgpu_mem *ctx_mem); #endif diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c index 3ba6d5ba5..590550004 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c @@ -54,28 +54,6 @@ void gm20b_ctxsw_prog_set_patch_addr(struct gk20a *g, ctxsw_prog_main_image_patch_adr_hi_o(), u64_hi32(addr)); } -void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, - struct nvgpu_mem *ctx_mem) -{ - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_num_save_ops_o(), 0); - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_num_restore_ops_o(), 0); -} - -void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, - struct nvgpu_mem *ctx_mem) -{ - u32 data; - - data = nvgpu_mem_rd(g, ctx_mem, ctxsw_prog_main_image_misc_options_o()); - - data = data & ~ctxsw_prog_main_image_misc_options_verif_features_m(); - data = data | ctxsw_prog_main_image_misc_options_verif_features_disabled_f(); - - nvgpu_mem_wr(g, ctx_mem, ctxsw_prog_main_image_misc_options_o(), data); -} - #ifdef CONFIG_NVGPU_GRAPHICS void gm20b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr) diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c index b6aa5d15b..cd64ff0d0 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c @@ -95,3 +95,24 @@ void gp10b_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g, ctxsw_prog_main_image_compute_preemption_options_o())); } #endif + +#ifdef CONFIG_NVGPU_HAL_NON_FUSA +void gp10b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, + struct nvgpu_mem *ctx_mem) +{ + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_num_wfi_save_ops_o(), 0); + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_num_cta_save_ops_o(), 0); +#ifdef CONFIG_NVGPU_GRAPHICS + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_num_gfxp_save_ops_o(), 0); +#endif +#ifdef CONFIG_NVGPU_CILP + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_num_cilp_save_ops_o(), 0); +#endif + + gm20b_ctxsw_prog_init_ctxsw_hdr_data(g, ctx_mem); +} +#endif diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h index 994bc693c..fd3353356 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h @@ -30,8 +30,10 @@ struct nvgpu_mem; void gp10b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g, struct nvgpu_mem *ctx_mem); +#ifdef CONFIG_NVGPU_HAL_NON_FUSA void gp10b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *ctx_mem); +#endif #ifdef CONFIG_NVGPU_GFXP void gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp(struct gk20a *g, struct nvgpu_mem *ctx_mem); diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c index 235889ee2..321df80c4 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c @@ -41,25 +41,6 @@ void gp10b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g, #endif } -void gp10b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, - struct nvgpu_mem *ctx_mem) -{ - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_num_wfi_save_ops_o(), 0); - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_num_cta_save_ops_o(), 0); -#ifdef CONFIG_NVGPU_GRAPHICS - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_num_gfxp_save_ops_o(), 0); -#endif -#ifdef CONFIG_NVGPU_CILP - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_num_cilp_save_ops_o(), 0); -#endif - - gm20b_ctxsw_prog_init_ctxsw_hdr_data(g, ctx_mem); -} - #ifdef CONFIG_NVGPU_GFXP void gp10b_ctxsw_prog_set_graphics_preemption_mode_gfxp(struct gk20a *g, struct nvgpu_mem *ctx_mem) diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index 7baaf9ba5..43019500c 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -444,13 +444,15 @@ static const struct gops_gr_ctxsw_prog ga100_ops_gr_ctxsw_prog = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_HAL_NON_FUSA + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, +#endif #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, #endif - .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, #ifdef CONFIG_NVGPU_GRAPHICS diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 455db457b..bec91d969 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -408,13 +408,15 @@ static const struct gops_gr_ctxsw_prog ga10b_ops_gr_ctxsw_prog = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_HAL_NON_FUSA + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, +#endif #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, #endif - .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, #ifdef CONFIG_NVGPU_GRAPHICS diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 3cd6de639..d83ec0db7 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -199,13 +199,15 @@ static const struct gops_gr_ctxsw_prog gm20b_ops_gr_ctxsw_prog = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, - .init_ctxsw_hdr_data = gm20b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gm20b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_HAL_NON_FUSA + .init_ctxsw_hdr_data = gm20b_ctxsw_prog_init_ctxsw_hdr_data, + .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, +#endif #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, #endif - .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index b2685614f..7dd6e3c46 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -254,13 +254,15 @@ static const struct gops_gr_ctxsw_prog gp10b_ops_gr_ctxsw_prog = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_HAL_NON_FUSA + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, +#endif #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, #endif - .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 53a5c6ab3..ca06e1630 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -331,13 +331,15 @@ static const struct gops_gr_ctxsw_prog gv11b_ops_gr_ctxsw_prog = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_HAL_NON_FUSA + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, +#endif #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, #endif - .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, #ifdef CONFIG_NVGPU_GRAPHICS diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index b37f1a326..bcf40d40c 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -375,13 +375,15 @@ static const struct gops_gr_ctxsw_prog tu104_ops_gr_ctxsw_prog = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_HAL_NON_FUSA + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, +#endif #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, #endif - .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, #ifdef CONFIG_NVGPU_GRAPHICS diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c index ff2d85228..8b5f4bf37 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c @@ -278,13 +278,15 @@ static const struct gops_gr_ctxsw_prog vgpu_ga10b_ops_gr_ctxsw_prog = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_HAL_NON_FUSA + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, +#endif #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, #endif - .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c index b3dc195a7..5335c1263 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c @@ -249,13 +249,15 @@ static const struct gops_gr_ctxsw_prog vgpu_gv11b_ops_gr_ctxsw_prog = { .get_patch_count = gm20b_ctxsw_prog_get_patch_count, .set_patch_count = gm20b_ctxsw_prog_set_patch_count, .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, - .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_HAL_NON_FUSA + .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, + .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, +#endif #ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, #endif - .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr, .set_zcull = gm20b_ctxsw_prog_set_zcull, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index 3900d70a2..5428690eb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -915,10 +915,12 @@ struct gops_gr_ctxsw_prog { struct nvgpu_mem *ctx_mem, u64 addr); #endif +#ifdef CONFIG_NVGPU_HAL_NON_FUSA void (*disable_verif_features)(struct gk20a *g, struct nvgpu_mem *ctx_mem); void (*init_ctxsw_hdr_data)(struct gk20a *g, struct nvgpu_mem *ctx_mem); +#endif #ifdef CONFIG_NVGPU_GRAPHICS void (*set_zcull_ptr)(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); diff --git a/userspace/units/gr/obj_ctx/nvgpu-gr-obj-ctx.h b/userspace/units/gr/obj_ctx/nvgpu-gr-obj-ctx.h index af33013ad..5c15a805b 100644 --- a/userspace/units/gr/obj_ctx/nvgpu-gr-obj-ctx.h +++ b/userspace/units/gr/obj_ctx/nvgpu-gr-obj-ctx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -60,8 +60,6 @@ struct unit_module; * nvgpu_gr_obj_ctx_set_golden_image_size, * nvgpu_gr_obj_ctx_commit_global_ctx_buffers, * nvgpu_gr_ctx_init_compute_preemption_mode, - * gp10b_ctxsw_prog_init_ctxsw_hdr_data, - * gm20b_ctxsw_prog_init_ctxsw_hdr_data, * gv11b_ctxsw_prog_set_context_buffer_ptr, * gv11b_ctxsw_prog_set_type_per_veid_header, * gp10b_gr_init_get_ctx_attrib_cb_size, diff --git a/userspace/units/gr/setup/nvgpu-gr-setup.h b/userspace/units/gr/setup/nvgpu-gr-setup.h index 58e7ac7bc..11e71d21e 100644 --- a/userspace/units/gr/setup/nvgpu-gr-setup.h +++ b/userspace/units/gr/setup/nvgpu-gr-setup.h @@ -59,7 +59,6 @@ struct unit_module; * gops_gr_setup.alloc_obj_ctx, * nvgpu_gr_ctx_load_golden_ctx_image, * gm20b_ctxsw_prog_set_patch_addr, - * gm20b_ctxsw_prog_disable_verif_features, * gv11b_gr_init_commit_global_attrib_cb, * gm20b_gr_init_commit_global_attrib_cb, * gv11b_gr_init_commit_global_timeslice,