diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 644d6dee8..4173278f4 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -406,7 +406,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ common/vgpu/ce_vgpu.o \ common/vgpu/mm/mm_vgpu.o \ common/vgpu/mm/vm_vgpu.o \ - common/vgpu/mm/vgpu_mm_gp10b.o \ common/vgpu/vgpu.o \ common/vgpu/debugger_vgpu.o \ common/vgpu/tsg_vgpu.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 9876dc627..d04fd1788 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -313,7 +313,6 @@ srcs += common/sim.c \ common/vgpu/fecs_trace_vgpu.c \ common/vgpu/mm/mm_vgpu.c \ common/vgpu/mm/vm_vgpu.c \ - common/vgpu/mm/vgpu_mm_gp10b.c \ common/vgpu/gr/gr_vgpu.c \ common/vgpu/gr/ctx_vgpu.c \ common/vgpu/clk_vgpu.c \ diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c index d813984a2..a198c8a8a 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c @@ -54,7 +54,6 @@ #include "common/vgpu/perf/cyclestats_snapshot_vgpu.h" #include "gp10b/gp10b.h" #include "gp10b/hal_gp10b.h" -#include "common/vgpu/mm/vgpu_mm_gp10b.h" #include "vgpu_fuse_gp10b.h" #include "common/falcon/falcon_gk20a.h" @@ -482,7 +481,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { - .gmmu_map = vgpu_gp10b_locked_gmmu_map, + .gmmu_map = vgpu_locked_gmmu_map, .gmmu_unmap = vgpu_locked_gmmu_unmap, .vm_bind_channel = vgpu_vm_bind_channel, .fb_flush = vgpu_mm_fb_flush, @@ -496,7 +495,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_iommu_bit = gk20a_mm_get_iommu_bit, .get_mmu_levels = gp10b_mm_get_mmu_levels, .init_pdb = gp10b_mm_init_pdb, - .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, + .init_mm_setup_hw = NULL, .is_bar1_supported = gm20b_mm_is_bar1_supported, .init_inst_block = gk20a_init_inst_block, .mmu_fault_pending = NULL, diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c index f84ca8f09..ab55b42b7 100644 --- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c @@ -65,7 +65,6 @@ #include "common/vgpu/fecs_trace_vgpu.h" #include "common/vgpu/perf/cyclestats_snapshot_vgpu.h" #include "common/vgpu/fifo/vgpu_fifo_gv11b.h" -#include "common/vgpu/mm/vgpu_mm_gp10b.h" #include "common/falcon/falcon_gk20a.h" @@ -555,7 +554,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { - .gmmu_map = vgpu_gp10b_locked_gmmu_map, + .gmmu_map = vgpu_locked_gmmu_map, .gmmu_unmap = vgpu_locked_gmmu_unmap, .vm_bind_channel = vgpu_vm_bind_channel, .fb_flush = vgpu_mm_fb_flush, @@ -569,7 +568,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_iommu_bit = gk20a_mm_get_iommu_bit, .get_mmu_levels = gp10b_mm_get_mmu_levels, .init_pdb = gp10b_mm_init_pdb, - .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, + .init_mm_setup_hw = NULL, .is_bar1_supported = gv11b_mm_is_bar1_supported, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = NULL, diff --git a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c index 45dbc1ce8..4c9d9cf70 100644 --- a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.c @@ -27,7 +27,9 @@ #include #include #include +#include +#include #include #include "mm_vgpu.h" @@ -249,3 +251,197 @@ void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); } + +static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, + u64 addr, u64 size, size_t *oob_size) +{ + if (*oob_size < sizeof(*mem_desc)) { + return -ENOMEM; + } + + mem_desc->addr = addr; + mem_desc->length = size; + *oob_size -= sizeof(*mem_desc); + return 0; +} + +u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, + u64 map_offset, + struct nvgpu_sgt *sgt, + u64 buffer_offset, + u64 size, + u32 pgsz_idx, + u8 kind_v, + u32 ctag_offset, + u32 flags, + enum gk20a_mem_rw_flag rw_flag, + bool clear_ctags, + bool sparse, + bool priv, + struct vm_gk20a_mapping_batch *batch, + enum nvgpu_aperture aperture) +{ + int err = 0; + struct gk20a *g = gk20a_from_vm(vm); + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; + struct tegra_vgpu_mem_desc *mem_desc; + u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; + u64 buffer_size = ALIGN(size, SZ_4K); + u64 space_to_skip = buffer_offset; + u32 mem_desc_count = 0, i; + void *handle = NULL; + size_t oob_size; + u8 prot; + struct nvgpu_sgl *sgl; + + nvgpu_log_fn(g, " "); + + /* FIXME: add support for sparse mappings */ + + if (!sgt) { + nvgpu_do_assert_print(g, "NULL SGT"); + return 0; + } + + if (nvgpu_iommuable(g)) { + nvgpu_do_assert_print(g, "MM should not be IOMMU-able"); + return 0; + } + + if (space_to_skip & (page_size - 1)) { + return 0; + } + + (void) memset(&msg, 0, sizeof(msg)); + + /* Allocate (or validate when map_offset != 0) the virtual address. */ + if (!map_offset) { + map_offset = nvgpu_vm_alloc_va(vm, size, pgsz_idx); + if (!map_offset) { + nvgpu_err(g, "failed to allocate va space"); + err = -ENOMEM; + goto fail; + } + } + + handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(), + TEGRA_VGPU_QUEUE_CMD, + (void **)&mem_desc, &oob_size); + if (!handle) { + err = -EINVAL; + goto fail; + } + sgl = sgt->sgl; + + /* Align size to page size */ + size = ALIGN(size, page_size); + + while (sgl) { + u64 phys_addr; + u64 chunk_length; + + /* + * Cut out sgl ents for space_to_skip. + */ + if (space_to_skip && + space_to_skip >= nvgpu_sgt_get_length(sgt, sgl)) { + space_to_skip -= nvgpu_sgt_get_length(sgt, sgl); + sgl = nvgpu_sgt_get_next(sgt, sgl); + continue; + } + + phys_addr = nvgpu_sgt_get_phys(g, sgt, sgl) + space_to_skip; + chunk_length = min(size, + nvgpu_sgt_get_length(sgt, sgl) - space_to_skip); + + if (add_mem_desc(&mem_desc[mem_desc_count++], phys_addr, + chunk_length, &oob_size)) { + err = -ENOMEM; + goto fail; + } + + space_to_skip = 0; + size -= chunk_length; + sgl = nvgpu_sgt_get_next(sgt, sgl); + + if (size == 0) { + break; + } + } + + if (rw_flag == gk20a_mem_flag_read_only) { + prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; + } else if (rw_flag == gk20a_mem_flag_write_only) { + prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; + } else { + prot = TEGRA_VGPU_MAP_PROT_NONE; + } + + if (pgsz_idx == GMMU_PAGE_SIZE_KERNEL) { + if (page_size == vm->gmmu_page_sizes[GMMU_PAGE_SIZE_SMALL]) { + pgsz_idx = GMMU_PAGE_SIZE_SMALL; + } else if (page_size == + vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG]) { + pgsz_idx = GMMU_PAGE_SIZE_BIG; + } else { + nvgpu_err(g, "invalid kernel page size %d", + page_size); + goto fail; + } + } + + msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; + msg.handle = vgpu_get_handle(g); + p->handle = vm->handle; + p->gpu_va = map_offset; + p->size = buffer_size; + p->mem_desc_count = mem_desc_count; + p->pgsz_idx = pgsz_idx; + p->iova = 0; + p->kind = kind_v; + if (flags & NVGPU_VM_MAP_CACHEABLE) { + p->flags = TEGRA_VGPU_MAP_CACHEABLE; + } + if (flags & NVGPU_VM_MAP_IO_COHERENT) { + p->flags |= TEGRA_VGPU_MAP_IO_COHERENT; + } + if (flags & NVGPU_VM_MAP_L3_ALLOC) { + p->flags |= TEGRA_VGPU_MAP_L3_ALLOC; + } + if (flags & NVGPU_VM_MAP_PLATFORM_ATOMIC) { + p->flags |= TEGRA_VGPU_MAP_PLATFORM_ATOMIC; + } + + p->prot = prot; + p->ctag_offset = ctag_offset; + p->clear_ctags = clear_ctags; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + if (err || msg.ret) { + goto fail; + } + + /* TLB invalidate handled on server side */ + + vgpu_ivc_oob_put_ptr(handle); + return map_offset; +fail: + if (handle) { + vgpu_ivc_oob_put_ptr(handle); + } + nvgpu_err(g, "Failed: err=%d, msg.ret=%d", err, msg.ret); + nvgpu_err(g, + " Map: %-5s GPU virt %#-12llx +%#-9llx " + "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | " + "kind=%#02x APT=%-6s", + vm->name, map_offset, buffer_size, buffer_offset, + vm->gmmu_page_sizes[pgsz_idx] >> 10, + nvgpu_gmmu_perm_str(rw_flag), + kind_v, "SYSMEM"); + for (i = 0; i < mem_desc_count; i++) { + nvgpu_err(g, " > 0x%010llx + 0x%llx", + mem_desc[i].addr, mem_desc[i].length); + } + + return 0; +} diff --git a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.h b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.h index 6eb20c151..00663e258 100644 --- a/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.h +++ b/drivers/gpu/nvgpu/common/vgpu/mm/mm_vgpu.h @@ -29,6 +29,8 @@ struct vm_gk20a_mapping_batch; struct gk20a_as_share; struct vm_gk20a; enum gk20a_mem_rw_flag; +struct nvgpu_sgt; +enum nvgpu_aperture; void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, u64 vaddr, @@ -45,4 +47,19 @@ void vgpu_mm_l2_invalidate(struct gk20a *g); int vgpu_mm_l2_flush(struct gk20a *g, bool invalidate); int vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb); void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable); +u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, + u64 map_offset, + struct nvgpu_sgt *sgt, + u64 buffer_offset, + u64 size, + u32 pgsz_idx, + u8 kind_v, + u32 ctag_offset, + u32 flags, + enum gk20a_mem_rw_flag rw_flag, + bool clear_ctags, + bool sparse, + bool priv, + struct vm_gk20a_mapping_batch *batch, + enum nvgpu_aperture aperture); #endif /* NVGPU_MM_VGPU_H */ diff --git a/drivers/gpu/nvgpu/common/vgpu/mm/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/mm/vgpu_mm_gp10b.c deleted file mode 100644 index 54defb479..000000000 --- a/drivers/gpu/nvgpu/common/vgpu/mm/vgpu_mm_gp10b.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Virtualized GPU Memory Management - * - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include - -#include "vgpu_mm_gp10b.h" -#include "gk20a/mm_gk20a.h" - -int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) -{ - g->mm.disable_bigpage = true; - return 0; -} - -static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, - u64 addr, u64 size, size_t *oob_size) -{ - if (*oob_size < sizeof(*mem_desc)) { - return -ENOMEM; - } - - mem_desc->addr = addr; - mem_desc->length = size; - *oob_size -= sizeof(*mem_desc); - return 0; -} - -u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, - u64 map_offset, - struct nvgpu_sgt *sgt, - u64 buffer_offset, - u64 size, - u32 pgsz_idx, - u8 kind_v, - u32 ctag_offset, - u32 flags, - enum gk20a_mem_rw_flag rw_flag, - bool clear_ctags, - bool sparse, - bool priv, - struct vm_gk20a_mapping_batch *batch, - enum nvgpu_aperture aperture) -{ - int err = 0; - struct gk20a *g = gk20a_from_vm(vm); - struct tegra_vgpu_cmd_msg msg; - struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; - struct tegra_vgpu_mem_desc *mem_desc; - u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; - u64 buffer_size = ALIGN(size, SZ_4K); - u64 space_to_skip = buffer_offset; - u32 mem_desc_count = 0, i; - void *handle = NULL; - size_t oob_size; - u8 prot; - struct nvgpu_sgl *sgl; - - nvgpu_log_fn(g, " "); - - /* FIXME: add support for sparse mappings */ - - if (!sgt) { - nvgpu_do_assert_print(g, "NULL SGT"); - return 0; - } - - if (nvgpu_iommuable(g)) { - nvgpu_do_assert_print(g, "MM should not be IOMMU-able"); - return 0; - } - - if (space_to_skip & (page_size - 1)) { - return 0; - } - - (void) memset(&msg, 0, sizeof(msg)); - - /* Allocate (or validate when map_offset != 0) the virtual address. */ - if (!map_offset) { - map_offset = nvgpu_vm_alloc_va(vm, size, pgsz_idx); - if (!map_offset) { - nvgpu_err(g, "failed to allocate va space"); - err = -ENOMEM; - goto fail; - } - } - - handle = vgpu_ivc_oob_get_ptr(vgpu_ivc_get_server_vmid(), - TEGRA_VGPU_QUEUE_CMD, - (void **)&mem_desc, &oob_size); - if (!handle) { - err = -EINVAL; - goto fail; - } - sgl = sgt->sgl; - - /* Align size to page size */ - size = ALIGN(size, page_size); - - while (sgl) { - u64 phys_addr; - u64 chunk_length; - - /* - * Cut out sgl ents for space_to_skip. - */ - if (space_to_skip && - space_to_skip >= nvgpu_sgt_get_length(sgt, sgl)) { - space_to_skip -= nvgpu_sgt_get_length(sgt, sgl); - sgl = nvgpu_sgt_get_next(sgt, sgl); - continue; - } - - phys_addr = nvgpu_sgt_get_phys(g, sgt, sgl) + space_to_skip; - chunk_length = min(size, - nvgpu_sgt_get_length(sgt, sgl) - space_to_skip); - - if (add_mem_desc(&mem_desc[mem_desc_count++], phys_addr, - chunk_length, &oob_size)) { - err = -ENOMEM; - goto fail; - } - - space_to_skip = 0; - size -= chunk_length; - sgl = nvgpu_sgt_get_next(sgt, sgl); - - if (size == 0) { - break; - } - } - - if (rw_flag == gk20a_mem_flag_read_only) { - prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; - } else if (rw_flag == gk20a_mem_flag_write_only) { - prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; - } else { - prot = TEGRA_VGPU_MAP_PROT_NONE; - } - - if (pgsz_idx == GMMU_PAGE_SIZE_KERNEL) { - if (page_size == vm->gmmu_page_sizes[GMMU_PAGE_SIZE_SMALL]) { - pgsz_idx = GMMU_PAGE_SIZE_SMALL; - } else if (page_size == - vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG]) { - pgsz_idx = GMMU_PAGE_SIZE_BIG; - } else { - nvgpu_err(g, "invalid kernel page size %d", - page_size); - goto fail; - } - } - - msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; - msg.handle = vgpu_get_handle(g); - p->handle = vm->handle; - p->gpu_va = map_offset; - p->size = buffer_size; - p->mem_desc_count = mem_desc_count; - p->pgsz_idx = pgsz_idx; - p->iova = 0; - p->kind = kind_v; - if (flags & NVGPU_VM_MAP_CACHEABLE) { - p->flags = TEGRA_VGPU_MAP_CACHEABLE; - } - if (flags & NVGPU_VM_MAP_IO_COHERENT) { - p->flags |= TEGRA_VGPU_MAP_IO_COHERENT; - } - if (flags & NVGPU_VM_MAP_L3_ALLOC) { - p->flags |= TEGRA_VGPU_MAP_L3_ALLOC; - } - if (flags & NVGPU_VM_MAP_PLATFORM_ATOMIC) { - p->flags |= TEGRA_VGPU_MAP_PLATFORM_ATOMIC; - } - - p->prot = prot; - p->ctag_offset = ctag_offset; - p->clear_ctags = clear_ctags; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - if (err || msg.ret) { - goto fail; - } - - /* TLB invalidate handled on server side */ - - vgpu_ivc_oob_put_ptr(handle); - return map_offset; -fail: - if (handle) { - vgpu_ivc_oob_put_ptr(handle); - } - nvgpu_err(g, "Failed: err=%d, msg.ret=%d", err, msg.ret); - nvgpu_err(g, - " Map: %-5s GPU virt %#-12llx +%#-9llx " - "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | " - "kind=%#02x APT=%-6s", - vm->name, map_offset, buffer_size, buffer_offset, - vm->gmmu_page_sizes[pgsz_idx] >> 10, - nvgpu_gmmu_perm_str(rw_flag), - kind_v, "SYSMEM"); - for (i = 0; i < mem_desc_count; i++) { - nvgpu_err(g, " > 0x%010llx + 0x%llx", - mem_desc[i].addr, mem_desc[i].length); - } - - return 0; -} diff --git a/drivers/gpu/nvgpu/common/vgpu/mm/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/common/vgpu/mm/vgpu_mm_gp10b.h deleted file mode 100644 index f314c1c5c..000000000 --- a/drivers/gpu/nvgpu/common/vgpu/mm/vgpu_mm_gp10b.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef NVGPU_VGPU_MM_GP10B_H -#define NVGPU_VGPU_MM_GP10B_H - -#include - -struct gk20a; -struct vm_gk20a; -struct nvgpu_sgt; -struct vm_gk20a_mapping_batch; - -enum gk20a_mem_rw_flag; -enum nvgpu_aperture; - -u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, - u64 map_offset, - struct nvgpu_sgt *sgt, - u64 buffer_offset, - u64 size, - u32 pgsz_idx, - u8 kind_v, - u32 ctag_offset, - u32 flags, - enum gk20a_mem_rw_flag rw_flag, - bool clear_ctags, - bool sparse, - bool priv, - struct vm_gk20a_mapping_batch *batch, - enum nvgpu_aperture aperture); -int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g); - -#endif /* NVGPU_VGPU_MM_GP10B_H */ diff --git a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c index 4e7e7221c..e1a8a65cb 100644 --- a/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c +++ b/drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c @@ -96,6 +96,7 @@ static void vgpu_init_vars(struct gk20a *g, struct gk20a_platform *platform) nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, platform->can_railgate_init); g->railgate_delay = platform->railgate_delay_init; + g->mm.disable_bigpage = true; nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES, platform->unify_address_spaces); }