From 72f0c2237795535df202bf74872be9ab1d8f7658 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Fri, 21 Jun 2019 14:59:53 -0700 Subject: [PATCH] gpu: nvgpu: Fix MISRA 10.3 error in common.gr unit Fix MISRA C-2012 Rule 10.3 error in common.gr unit misra_c_2012_rule_10_3_violation: Implicit conversion of "!!(gr->ctxsw_disable_count < 0)" from essential type "boolean" to different or narrower essential type "signed 32-bit int". Jira NVGPU-3622 Change-Id: I27fb1aa64906242230678dff345307eb0a2d7bdc Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2140940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/gr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index 032eae8b9..cb3d9ba8e 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -775,7 +776,7 @@ int nvgpu_gr_enable_ctxsw(struct gk20a *g) goto ctxsw_already_enabled; } gr->ctxsw_disable_count--; - WARN_ON(gr->ctxsw_disable_count < 0); + nvgpu_assert(gr->ctxsw_disable_count >= 0); if (gr->ctxsw_disable_count == 0) { err = g->ops.gr.falcon.ctrl_ctxsw(g, NVGPU_GR_FALCON_METHOD_CTXSW_START, 0U, NULL);