gpu: nvgpu: vgpu: add vgpu_gv11b_tsg_bind_channel

Add TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX command to pass subctx_id
and runqueu_sel to RM server. Use this command in gv11b's
implementation of gops->fifo.tsg_bind_channel.

Jira EVLR-1751

Change-Id: I8ba69c95ea1c6bb7fa106588b6420ed543b2386b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1579840
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -41,5 +41,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
 	vgpu/gv11b/vgpu_hal_gv11b.o \
 	vgpu/gv11b/vgpu_gr_gv11b.o \
 	vgpu/gv11b/vgpu_fifo_gv11b.o \
-	vgpu/gv11b/vgpu_subctx_gv11b.o
+	vgpu/gv11b/vgpu_subctx_gv11b.o \
+	vgpu/gv11b/vgpu_tsg_gv11b.o
 endif

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -81,6 +81,7 @@
 #include "vgpu_gr_gv11b.h"
 #include "vgpu_fifo_gv11b.h"
 #include "vgpu_subctx_gv11b.h"
+#include "vgpu_tsg_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
@@ -377,7 +378,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers,
 		.deinit_eng_method_buffers =
 			gv11b_fifo_deinit_eng_method_buffers,
-		.tsg_bind_channel = vgpu_tsg_bind_channel,
+		.tsg_bind_channel = vgpu_gv11b_tsg_bind_channel,
 		.tsg_unbind_channel = vgpu_tsg_unbind_channel,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
 		.alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/tegra_vgpu.h>
+#include <gk20a/gk20a.h>
+#include <vgpu/vgpu.h>
+
+#include "vgpu_tsg_gv11b.h"
+
+int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
+				struct channel_gk20a *ch)
+{
+	struct tegra_vgpu_cmd_msg msg = {};
+	struct tegra_vgpu_tsg_bind_channel_ex_params *p =
+				&msg.params.t19x.tsg_bind_channel_ex;
+	int err;
+
+	gk20a_dbg_fn("");
+
+	err = gk20a_tsg_bind_channel(tsg, ch);
+	if (err)
+		return err;
+
+	msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX;
+	msg.handle = vgpu_get_handle(tsg->g);
+	p->tsg_id = tsg->tsgid;
+	p->ch_handle = ch->virt_ctx;
+	p->subctx_id = ch->t19x.subctx_id;
+	p->runqueue_sel = ch->t19x.runqueue_sel;
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	err = err ? err : msg.ret;
+	if (err) {
+		nvgpu_err(tsg->g,
+			"vgpu_gv11b_tsg_bind_channel failed, ch %d tsgid %d",
+			ch->chid, tsg->tsgid);
+		gk20a_tsg_unbind_channel(ch);
+	}
+
+	return err;
+}

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _VGPU_TSG_GV11B_H_
+#define _VGPU_TSG_GV11B_H_
+
+int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg,
+				struct channel_gk20a *ch);
+
+#endif

include/linux/tegra_vgpu_t19x.h

@@ -17,6 +17,7 @@
 #define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER		100
 #define TEGRA_VGPU_CMD_FREE_CTX_HEADER		101
 #define TEGRA_VGPU_CMD_MAP_SYNCPT		102
+#define TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX 	103
 
 struct tegra_vgpu_alloc_ctx_header_params {
 	u64 ch_handle;
@@ -35,10 +36,18 @@ struct tegra_vgpu_map_syncpt_params {
 	u8 prot;
 };
 
+struct tegra_vgpu_tsg_bind_channel_ex_params {
+	u32 tsg_id;
+	u64 ch_handle;
+	u32 subctx_id;
+	u32 runqueue_sel;
+};
+
 union tegra_vgpu_t19x_params {
 	struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header;
 	struct tegra_vgpu_free_ctx_header_params free_ctx_header;
 	struct tegra_vgpu_map_syncpt_params map_syncpt;
+	struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex;
 };
 
 #define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT	100