From 7522c3ee31630bcd34ab0e128986d4b25f485df9 Mon Sep 17 00:00:00 2001 From: Austin Tajiri Date: Wed, 19 Apr 2023 18:37:35 +0000 Subject: [PATCH] gpu: nvgpu: skip security check in ctxsw init Force ctxsw ucode to skip the security level check by clearing mailbox 1 before starting FECS/GPCCS. Jira NVGPU-9217 Change-Id: Id4286d0882a29a849128e62c5421c8ae6071e3b1 Signed-off-by: Austin Tajiri Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2891013 Reviewed-by: svcacv Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Rajesh Devaraj Reviewed-by: Vaibhav Kachore GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index 8b715b97f..f0772797e 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -199,6 +199,12 @@ void gm20b_gr_falcon_start_ucode(struct gk20a *g) g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 0U, (~U32(0U))); + /* + * When GPCCS and FECS are booted in NS mode, clear mailbox 1 to skip + * the security level check in ucode. + */ + g->ops.gr.falcon.fecs_ctxsw_clear_mailbox(g, 1U, (~U32(0U))); + nvgpu_writel(g, gr_gpccs_dmactl_r(), gr_gpccs_dmactl_require_ctx_f(0U)); nvgpu_writel(g, gr_fecs_dmactl_r(), gr_fecs_dmactl_require_ctx_f(0U));